how to send 2 byte of data through uart

Hi,

I need to send 2 bytes of data thorough uart.

But by standard protocol I can send only 1 byte of data.

I am using some code like this for send 1 byte.



when I am trying to send 2 bytes of data, I should again go to stReceive from stStop.

But when I am trying it the uart data is transmitting continuously

Can anyone suggest me, how can I do that for transmitting 2 bytes of data


Thanks in adavance
xilinx1001

You need a counter! And should do something like:


Alternatively you can use a state machine. In state 0, you send byte 1, in state 1 you send byte 2, in state 3 you don't send anything.

You also need some kind of flag to signal that the uart transmission is complete, so you can put the next byte.

Hi,

Thank you for ur reply.
Yes, you idea is nice. But I need to transmit data when ever I press s.
Can you give me suggestion about this

Thanks in adavance
xilinx1001

Yes, reset the counter every time you press s.

If s is a character you receive on uart, just compare the received characters with the value of s (in ascii "s" is 0x73) and when they match, reset counter, or state machine if you go that way.

Hi,

Thanks for ur reply.

what is read signal(rdsig) and write signal (wrsig) in UART?

When I need to make these signal 0 and1


Thanks in adavance
xilinx1001

It is right there in the description.

Hi,

I wrote the code something like this which is not working

please comment on it


when s1 =>
rdSig <= '0';
wrSig <= '0';

if rdaSig = '1' then
if dbOutSig <= X"73" then
dbInSig <= cm( 15 downto 8) ;
next_state <= s2;
else
next_state <= s1;

end if ;


-- if rdaSig = '1' then

if dbOutSig <= X"74" then

dbInsig <= cm2( 15 downto 8) ;
next_state <= s2;
else
next_state <= s1;

end if;
end if ;

when s2 =>
rdSig <= '0';
wrSig <= '1';
next_state <= s3 ;


when s3 =>

rdSig <= '1';
wrSig <= '0';


if rdaSig = '1' then
if dbOutSig <= X"73" then

dbInSig <= cm ( 7 downto 0 ) ;
next_state <= s4;
else
next_state <= s3;
end if ;



if dbOutSig <= X"74" then
dbInSig <= cm2( 7 downto 0 ) ;
next_state <= s4;
else
next_state <= s3;
end if ;
end if ;


when s4 =>
rdSig <= '0' ;
wrSig <= '1' ;
next_state <= s5 ;

when s5 =>
rdSig <= '1' ;
wrSig <= '0' ;
next_state <= s5 ;


end case;
end if ;
end process;