How to select the clock buffers in clock tree specification file?

[biju4u90]

In a discussion in this forum 3 years ago, it is seen that small size clock buffers will cause more delay and ocv issues whearas large ones consume more area and congestion. Somebody told to use medium sized buffers for clock tree whearas somebody else asked to use buffers with alternate drive strength! This is the link of the old discussion.

https://www.edaboard.com/threads/259845/

So..how should we select the clock buffers or inverters for CTS? Should we create the clock specification file by selecting all the available clock buffers and inverters or should we select them selectively?

 

[artmalik]

The choice of cells for clock tree is usually done according to the following
a) Balance of the rise/fall times of the inverters/buffers. If there is imbalance(determined by the tool), the tool rejects that cell.
b) The decision on buffer vs inverters was debate in older technologies....the newer technologies it is inverters.
c) inverters will be chosen by the tool because the new technologies(20nm,16nm....) .....
........ Nowadays it is not an important question anymore.... inverters+ tool decisions(cadence/synopsys) are smart enough to do the job

 

[biju4u90]

Suppose, in my library, there are 10 clock inverters available. Should I include all those clock inverters in the clock specification file or should I select a few among them? What is the criteria for selection of inverters in clock specification file? Is it like include all the available clock inverters in the clock specification file so that the tool selects the required ones intelligently for CTS?

 

[artmalik]

You don't need to do "any selection" of inverters.....if you are using cadence/synopsys tools you will be fine. There is no need to anything special. The tool will take care of it, you will see that the usage will be towards high drive strength of the inverters. Tools are smart enough to do all this.