how to select cell in clock generation file?

[quan228228]

Hi,

Now i design a clock divider. I know how to write verilog code to simulation,
But for tapout, we often write clock divider using gate cell.
My question is how to select gate cells? Is there any criteria?


Thanks!

/David

 

[quan228228]

Pls help!

thanks!

/david

 

[sameer_dlh25]

Hi David,

In the clock path broadly two things need to be taken care

1. duty cycle -> if in generated clock domain you want to preserve duty cycle(50 %) chosen cells in the clock paths must have same rise time and fall time. All the vendors provide such cell in their library( e.g. TSMC -> CKAND*)
2. After clock balancing in post layout there should not be glitch in the circuit due to delay mismatch .
I mean when you switch on the generated clock or your clock is running it's pulse width has to be maintained. Also make sure there is not anyglitch. To help balancing in backend you need to design a in FSM based clock divider( Search in Google/digital design books.)
I hope this will help

 

[quan228228]

Thanks!