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Re: How to run Pre-Sim using Synplify ASIC and ModelSim? Ple
In Digital design "PreSim"
means gate level without actually wireload
so if you already run RTL simulation (ModelSim or Debussy)
you need some kind synthesis EDA tools (such as Synopsys DC) and include the foundry cell library
after synthesis , you will get a gate level verilog file with library delay(setup,hold...)
put this file to your RTL simulation pattern to replace original RTL Code
this is what we call "PreSim'
so it's the same as you did in RTL Simulation.
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