how to run co-simulation on sigma-delta PLL? verilog+cadence

[eejli]

verilog spectre cosimulation

I have the verilog code for the sigma delta modulator and the PLL circuits in Cadence. How can I run the co-simulation on the whole PLL including the PLL circuits and the verilog code?

Thanks.

 

[jcpu]

sigma delta pll verilog

You might want to know simulation environment, SpectreVerilog.
In case of high level simulation, you can model analog part
with VHDL-A.
It can also perform gate level simulation in case your analog part
is described down to transistor. In which case, the computational speed
looks slow to me.

 

[eejli]

co simulation spectre and verilog

thanks.

Is there any document available to do this?

 

[jcchan]

Re: how to run co-simulation on sigma-delta PLL? verilog+cad

You can try synopsys nacosim

 

[jcpu]

Re: how to run co-simulation on sigma-delta PLL? verilog+cad

Procedure is a bit lengthy, that's the bitter part about Cadence.
And the speed is not that fast as we would imagine.

By googling, "spectre verilog" there are some class notes available
as example attached.

Good luck!