Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to run a pnoise analysis for PFD+CHP

Status
Not open for further replies.

knights

Member level 1
Member level 1
Joined
Oct 16, 2007
Messages
38
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,512
pnoise pfd cp

I want to do the phase noise analysis of the whole PLL. And try to
get the different parts phase noise seperate.
A pss+pnoise was done for my PFD plus CHP. The inputs of the PFD is two clk which made the CHP output average current close to 0 to simulate pll lock state.
The output connect to the LPF.And I measure the voltage of the CHP output .
The resutls shows that the phase noise is very big. Around -10-dBc@1kHz.

I think there is something wrong.

I check the thread https://www.designers-guide.org/Forum/YaBB.pl?num=1036525104/0

So I can not use direct plot phase noise. So I am confused how to set the pnoise analysis for this simualtion? especially the last item (jitter ,modulated, source .......)

Thanks.
 

pnoise analysis sources jitter

It is not correct to look at the pnoise of the signal at the LPF. As the signal magnitude(carrier) itself will be so less, it is bound to show unbelievable noise numbers. The way I do it is to connect a single pulse source to both the PFD inputs., connect the output of CP to a voltage source at midrange voltage (without the LPF) and look at the current noise in to the voltage source in steady state. This is the amount of noise the CP puts in to the LPF every cycle.
You can work this noise backwards take it to the PLL input and then multiply by the PLL transfer function to get the output noise., which will be N/Kp.
 

    knights

    Points: 2
    Helpful Answer Positive Rating
pnoise analysis

saro_k_82 said:
It is not correct to look at the pnoise of the signal at the LPF. As the signal magnitude(carrier) itself will be so less, it is bound to show unbelievable noise numbers. The way I do it is to connect a single pulse source to both the PFD inputs., connect the output of CP to a voltage source at midrange voltage (without the LPF) and look at the current noise in to the voltage source in steady state. This is the amount of noise the CP puts in to the LPF every cycle.
You can work this noise backwards take it to the PLL input and then multiply by the PLL transfer function to get the output noise., which will be N/Kp.


Thanks for your suggestion.
I think we measure the current noise output from CHP is right.But I can not set the output as current when do pnoise analysis.(See pic1) .My test circuit is show in pic2. And another question is how to set the noise type?
I check the cadence SpectreRF user guide, no detail was descriped about this setting.
Based on the setting in the pic1, I got the resutls shown in pic3. The pnoise and output noise is different. Is it because the unit is different? One is dB and another is dBc/Hz.

Any suggestions or discuss are highly appreciated.
 

pnoise noise type

The settings you have done is right., except that you need to give the input source as the pulse source supplying the up/dn clocks.
When you do it this way, you automatically get the current noise when you plot the output noise (the scale is A/sqrt(Hz))
The phase noise is output noise relative to the carrier, so obviously both will not be the same.
Here you shouldnt be looking at the phase noise., take the output noise multiply it by N/Icp to get the PFD-CP contribution to the PLL noise
 

simulating pfd/cp pnoise

saro_k_82 said:
The settings you have done is right., except that you need to give the input source as the pulse source supplying the up/dn clocks.
When you do it this way, you automatically get the current noise when you plot the output noise (the scale is A/sqrt(Hz))
The phase noise is output noise relative to the carrier, so obviously both will not be the same.
Here you shouldnt be looking at the phase noise., take the output noise multiply it by N/Icp to get the PFD-CP contribution to the PLL noise

Thanks ,It is a great help for me.
 

pnoise input source

saro_k_82 said:
The settings you have done is right., except that you need to give the input source as the pulse source supplying the up/dn clocks.
When you do it this way, you automatically get the current noise when you plot the output noise (the scale is A/sqrt(Hz))
The phase noise is output noise relative to the carrier, so obviously both will not be the same.
Here you shouldnt be looking at the phase noise., take the output noise multiply it by N/Icp to get the PFD-CP contribution to the PLL noise

Hello,

In this pnoise simulation table, i found an additional setting item: reference side band. what does this mean? and what value should I put for PFD/CP pnoise simulation?

Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top