How to Resolve this for loop error..

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Sasi Cm

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Code: 
module encc(a,b,c,clk,temp);
input [0:499]a;
input clk;
output [0:4]temp;
reg [0:4]temp;
output [0:4]b;
output [0:1]c;
reg [0:4]b;
reg [0:1]c;
integer m,n;
always @ (a)
assign b=a[0:4];
always @ (posedge clk)
begin
for(n=5;n<=499;n=n+5)
begin
for(m=9;m<=499;m=m+5)
begin
assign temp=b^a[5:10];
if(temp[0]!=1&&temp[1]!=1&&temp[2]!=1&&temp[3]!=1&&temp[4]!=1)
begin
c<=00;
end
else if(temp[0]!=0&&temp[1]!=0&&temp[2]!=0&&temp[3]!=0&&temp[4]!=0)
begin
c<=10;
end
else
begin
c<=11;
end
end
end
end
endmodule
 

it says that it is not possible to use a variable in the for loop....
 

I'd suggest your problem is using the "assign" keyword inside of a behavioral block ("always @" in this case).

Only use "assign" for a continuous assignment outside of such behavioral areas.
You should simply delete the "assign" statement for "temp" inside that always area.
(Note it is correct to use the blocking "=" for "temp", so that is good)

But, you should also have this same problem with the "assign" to "b", but you did not mention an error for that one?
To fix that, you could simply delete the "always @(a)" since it is not needed for continuous assignment to "b" (but do not remove the "assign")

Hope this is clear ...
BTW, I did not try to understand what you are actually trying to accomplish with this code, but it seems to me that in the end, "c" will always be determined by the value of "a[0:10]", so why all the "for-loop stuff?
(seems you are missing some indexing details for iterating through the rest of the "a" bits?)
 

Code Verilog - [expand]
1

else if(temp[0]!=0&&temp[1]!=0&&temp[2]!=0&&temp[3]!=0&&temp[4]!=0)


Not sure what you intend to do here.

0 && temp[1] etc are always going to be 0, so I think the above will always be false as 0 != 0 is a false statement. I think you should tell us in words what you are tying to do as your code probably doesn't even closely match what you want it to do. Are you trying to perform some check on how may bits are 1 or something?

Regards,
 

FvM said:
But due to operator precedence rules, the expression will be evaluated as (temp[0]!=0) && ... Just O.K.
Click to expand...
FvM,
I bet when it comes down to it the OP probably wanted to check if temp has any bits that are 1's temp != 4'b0 which I would have done as ~|temp using a reduction operator.

Sasi Cm,
I would rethink using [0:4] etc as packed values I would use [4:0] so your code matches what the rest of the world typically uses.
 

i try to do the following...
i have a length of sequence..Ex:1010 1110 1011 0001 1001 ........
now i save the first four bit as constant and i have to compare it with all remaining bits...
if both are eq,then i get output as 00,complement means 10 and neither eq nor complement means 11...
 

What I don't understand is why all of your buses are 5-bits in the code you posted (i.e. [0:4]) if you're only going to compare 4-bits?


If I'm interpreting this correctly...

Using the following sequence of nibbles 1010 1100 0110 0101 1000 1010 0001

we capture 1010 (the first nibble) and compare it to all subsequent nibbles..
const cmp out
1010 1100 11
1010 0110 11
1010 0101 01
1010 1000 11
1010 1010 00
1010 0001 11

If this is the case your compares should simply be...

Code Verilog - [expand]
1
2
3
4
5
6
7

if (const == cmp) begin
  out <= 2'b00;
end else if (const == ~cmp) begin
  out <= 2'b01;
end else begin
  out <= 2'b11;
end



regards
 
Last edited:

I have to say thanks for ur help....Really Thanks......
For example only i say four bits..the no. of bits r not a matter...
its simple for small length of sequence. In case of long length ,(range of 500 bits ) how can do these comparison. So i try the for loop. But its not working. Other wise i have to write else if statement for a long length......
 

Sasi Cm said:
In case of long length ,(range of 500 bits ) how can do these comparison. So i try the for loop. But its not working. Other wise i have to write else if statement for a long length......
Click to expand...
The sample of code I gave you was supposed to go inside a for loop. I'll leave it to you to figure out how to bit slice the parts you want to compare for each iteration of the loop. When synthesized the loop will be unraveled and the compares will occur in parallel, so you'll need your c output to be 500/5=100 entries wide (200-bits) not the 2-bits it currently is. Here is a a hint of how to perform the bit slice operation. http://www.esperan.com/view_tutorial.php?tutorialNumber=21

Regards
 

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