How to resolve the UCN -1 error in Design Compiler?

[ykk]

I have a block for 2's complement in Arithmetic module of a ALU. In the netlist synthesized by Synopsys Design compiler, I find that the 2's complement block output LSB is assigned to input LSB.
ie, assign y[0] = inp[0];
UCN -1 error due to multiple nets to inp. How can I rectify this?

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Code Verilog - [expand]
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module twos_comp(inp,x,y);
  input [7:0] inp;
  input x;
  output reg [7:0] y;
always @(inp or x)
begin
if (x)
y = (~inp) + 1'b1;
else
y = inp;
end
endmodule

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