How to Resolve the resonation of Coss and Leakage inductor at No Current output in a Phase Shifted Full bridge Converter?

Pulasthi_Perera

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I have been designing and testing a closed loop phase shifted full bridge.

When my Current Reference to the controller is 0A.bridge of the Phase shifted full bridge is switching at 50% with no overlapping. At this moment i observe high EMI induction in the Surroundings because in the Deadtime when one FET is open and other is also open but it Coss is charging to 400V.Now this Coss is resonates with the leakage inductance of the Transformer and produce EMI in the deadtime.

The Transformer primary waveform is attached and you can see the voltage spikes that are coupling to the secondary.
And my understanding of what is happening is drawn in the other attachment.

Can anybody did me on how to solve this issue? how can i Discharge the Coss of MOSFETS without delivering power to the secondary and prevent resonation.I see heavy EMI in this occation enough to make my monitor flicker.
 

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The OP means solve - but does not state what the desired outcome is ??

This is a classic problem for newbies with phase shift converters who want to run the output at near no load - it is a confluence of control and gate drive and the exact nature of the power stage - it can be solved - but a lot is needed to be known about all aspects of the converter.
 
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So OP , when you have absolutley no output load (apart from the vout divider), then your vout is steadily rising?
If it is rising, then how much load do you have to put there to stop it rising away?
If not rising then dont worry about it.
The EMC problem can be reduced by good tight layout , and shielding and "layout nannying" of the switching nodes.
Its like a DCM flyback during the FET off time the primary rings like mad..but not to worry...no one worries for this.

I take it you have RC snubbers on your sec diodes?

There are kind of active snubbers...where you have a snubber capacitor with a diode feeding into it....when the spike goes above a certain voltage then current goes into the cap (and so the cap kind of clamps the voltage low).....you then have a wee flyback converter to keep this cap discharged to a safe voltage for it....this can help reduce the kind of ring-up that you speak of. But i dont believe its really a problem.

But i am going to simulate this and get back to you. I am afraid i just dont beleive that in no load, your SMPS is causing so much noise that it interferes with your monitor. Please advise who told you this? If it was correct, the entire world of SMPS's would have to be banned...no one would ever pass an EMC test.

The attached simulates your situation in the free download LTspice...and shows that there is no problem that a bit of dummy load cant solve....or going into burst mode.....but burst mode is often not wanted when you have gate drive transformers (but thats another issue)
 

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There is also a PSFB in no load with ideal switches attached in LTspice ...this one doesnt suffer any spurious oncoming of the switchs and so there is much less power throughput at no load.
Though neither shows anything that could possibly be an EMC issue....certainly less EMC problem compared to when loaded.
 

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KlausST said:
explain "resolve".
Click to expand...
Thanks for the general definition. I knew it before.

Still I do have no explanation what it means for you / your application.

For the one: removing the C is a solution. No resonanace.
For the other: use it only with an according ohmic load.
For the other: add a damping circuit to attenuate the resoanance below a certain (unknown so far) level
For the next: a sign "out of order" is a solution.

You may find the "sign" as solution ridiculous. I did, too. But I experienced a similar situation first hand:
At a house with a two sided swing door, the door scratched on the floor when pushed, but only at one side only.
So they called a carpenter to fix it.

The carpenter just placed stickers "PUSH" and "PULL" to the door.. to use it only in the "non scratching" direction. Finished. It was his idea of a solution.
One can call him clever ... or lazy.

Klaus
 
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.ASC fails unless you include unknown Diode file.
Click to expand...
Sorry yes, the diodes may need replacing with whatever you have in your "palet", that came downloaded from Analog.com.
 

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Thanks, OP, please append diodes if you wish to. (didnt realise LTspice ever did that).
 

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Perhaps de-Q-ing the open load situation would get you to an "acceptable" ring-down that passes EMI mask (the ring note is always there but its duration is a scale factor in averaging type spectrum analyzers).

Add a load resistor across, that you can tolerate as a trade and observe?

See similar-but-not issues with LDOs that have to operate down to no load. Going from Class A to Class AB output is one way to go, lower feedback ladder Z is another (same as adding R load).

Wonder if there is a active clamp that could energize just long enough to scrub ringing and then let go, across the load. And whether that pain is worth it.
 

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It would be interesting if OP could upload a video clearly showing the monitor distortion happening with the PSFB on no load...then showing the monitor distortion being relieved when OP loads up the PSFB....but i very much doubt that such could even ever happen.

There is an issue with PSFB, that it can be somewhat inefficient in light load when in its simplest form....i think and suspect that this is what the OP is trying to get into(?), and is picking the no_load case "ringing" as a target to go for, for investigation, in order to try and do something about the light load inefficiency of PSFB...am i right?
 

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A few remarks:
Your scope waveform (I'm guessing this is the primary voltage measured with a diff probe) doesn't really show any "resonant" behavior. Hard to tell how much of the waveform is due to common mode feedthrough. Can you show scope captures of each half bridge output?
Under very light-load conditions some FETs will be turning on without ZVS, resulting in much higher dv/dt. I'm guessing this is the root cause of whatever EMI issue you're observing. You could try mitigating it by increasing the turn-on time of the FETs (by increasing the gate drive resistance in the high state).
You should also implement burst-mode control at light load, if you're not doing so already. This should overall reduce the number of switching cycles without ZVS, reducing EMI overall.

Pulasthi_Perera said:
Can anybody did me on how to solve this issue? how can i Discharge the Coss of MOSFETS without delivering power to the secondary and prevent resonation.
Click to expand...
It's unclear what you mean by "Discharge the Coss of MOSFETS". So long as there is bus voltage applied, there will always be some energy in some of the Coss.
Pulasthi_Perera said:
I see heavy EMI in this occation enough to make my monitor flicker.
Click to expand...
It's impossible to gauge how bad the EMI really is via a monitor flickering, especially if we won't know more about your setup (how and where your DUT is earthed, proximity to the monitor, load connections, etc). You should have a more quantitative measure of EMI. Some current transformers on your ground and line in connections may suffice, if you don't have access to a proper LISN.
 

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Vicor had a patent on their "near zaro current switching". A servo scheme that enforces a peak negative voltage that is small. Soft switching and then stomp the brake in time for a clean stop.
 

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Yes i have RC snubbers at sec SR FETs.the EMI issue that i talked about is occurred only at this occasion when zero current reference is given to the controller.Moniter screen gets turned off and when i give a positive current ref and current started flowing monitor turns back on.
--- Updated ---

yes definitely I'll give show you guys a video on my monitor issue.It only happens when zero current reference is at the controller.when i give a positive current reference it turns back on. I'll upload a video for you
--- Updated ---

mtwieg said:
It's unclear what you mean by "Discharge the Coss of MOSFETS". So long as there is bus voltage applied, there will always be some energy in some of the Coss.
Click to expand...
In a half bridge when on Mosfet is turned on, the other mosfet have a voltage stress of the input voltage of the bridge in this case 400V.So the Coss output capacitor of the that particular mosfet get charged to 400V.

when the first mosfet turned off and other mosfet turned off i have implemented a deadtime between the switching.

In that deadtime the both mosfets are turned off but the previously charged Coss Capacitor of the Mosfet now get discharged resonating with the transformer leakage inductance and delivers power to the secondary.

That is what can be seen in the oscilloscope waveform that i have attached
--- Updated ---

What is the purpose of these two diodes why these diodes are placed in the topology?
 

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Thanks, I think I understand your meaning now. Indeed, during the dead time the energy in Coss may be delivered to the load via the transformer. But that depends on the state of both bridges. If both bridges have exactly the same timings and no phase shift, then their output voltages should be identical, thus no voltage across the primary, and thus no power delivered either to the load or the leakage inductance. This is regardless of the value of Coss or the dead time.

It's unreasonable to expect an analog PWM controller to operate smoothly all the way down to zero phase shift (a digital PWM generator should have no problem). That's why I suggest burst mode. It allows you to set a minimum operating phase shift, below which the PWM will shut off entirely, thus ensuring you will only need to operate with soft switching.

I don't think that snubbers are the right way to address your issue. For a PSFB, snubbers should only be used to dampen the resonance formed by Coss and the parasitic inductance of each FET, not the resonance formed by Coss and the leakage inductance. So far I don't see any evidence that your problem is due to the former resonance (would need to see clean captures of each bridge output). If you're trying to snub the latter, then I think you're misunderstanding the entire point of the PSFB topology.
Pulasthi_Perera said:
What is the purpose of these two diodes why these diodes are placed in the topology?
Click to expand...
These clamping diodes on the primary are often used to reduce stress on the secondary side silicon (including ringing). See this document for an explanation. They might be helpful for you, hard to tell without a schematic or more scope captures.
 

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This is a good point, but means your series caps in your gdt (if you use GDT) will ring with the Lm of the GDT. ( due to the repeated sudden duty cycle change from 50% to nothing) This can cause spurious on-coming of the FETs.
Confessedly you may alternatively use bootstrap drive...but these are dodgy when the input bus is 400V+.
As is known , one of the great advantages of PSFB is that your FETs are always switched with 50% duty, (no matter what load) and this is excellent for using GDTs (gate drive transformers).
Bootstrap = deathtrap, as has been discussed much on this forum.

Has OP tried slwoign up the FET switch on, by using series gate resistors...this may do the trick....use a diode to turn the fets off. So you turn them off quicker.
PSFB shoudl ZVS switch at turn on....so it shouldnt matter too much that you have a slow switch on.
But as Easy Peasy has written here b4....smashing the fets off fast, with a cap across them, can be a good ploy to reduce switching losses.

Phase Shift Full Bridge SMPS is massively over-hyped?

Hello, The Phase Shift Full Bridge (PSFB) converter is a hoax. –The LTspice simulation attached of a “plain” Full Bridge SMPS bears this out. PSFB claims to be able to reduce switching losses compared to the “plain” Full Bridge SMPS. However the PSFB does have Turn-OFF switching losses, just...
www.edaboard.com
 
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These diodes are an industry standard approach to the high power Ph Sh FB, the inductor allows soft switching to lower loads - if the diodes were not there there would be a lot of high voltage high frequency ringing across the transformer - the diodes clamp this to the rails - often they have damping resistors in series to limit the residual ringing, there is a benefit of reduced snubbing needed on the output diodes too.
 

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mtwieg said:
If you're trying to snub the latter, then I think you're misunderstanding the entire point of the PSFB topology
Click to expand...
Nope I am not trying to snubber the latter. I already snubbed the Turn on ringing of the FETs but this here is a different issue.I can understand that snubbing won't solve it
cupoftea said:
Has OP tried slwoign up the FET switch on, by using series gate resistors.
Click to expand...
Yes i have a gate resistor of 5 ohms at the moment.
 

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