How to resolve adc sampling rate for the system

[curious_mind]

I have a control system modeled in matlab, which takes the inputs from ADC and then continues to process the data. Simulation works fine. In real world,I am not sure how to fix the sampling rate. ADC is a simultaneous sampling type (AD7606) and the fixed point algorithm runs in FPGA. I am using bunch of discrete integrator which requires the sampling time as a parameter. If I fix 10k as a sampling rate, I will never be able to get simultaneous data from ADC at this rate as the ADC requires more time to acquire data than 100us(10kHz). I am generating all control signals from FPGA and I am presuming that I use 10KHz as the clock source. (is that correct?)

Here is the Problem: How to maintain the same sample rate for adc and the control model and yet the data to the control model is available at every 100us

 

[KlausST]

Hi,

I´m not sure what you want to know.

--> If you want a 10kHz sampling rate then simply provide a 10kHz signal to the CONVST input. That´s it.

If I fix 10k as a sampling rate, I will never be able to get simultaneous data from ADC at this rate as the ADC requires more time to acquire data than 100us(10kHz).

It IS a simultaneously sampling ADC, thus you surely get simultaneous data

And according datasheet the conversion time is 4us with 1us acquisition time. So where does your "100us" come from?

***
For further discussion I recommendn yo to draw a sketch / timing diagram / whatever to better visualize your issue.

Klaus

 

[curious_mind]

The issue is that I need to fetch 4 data inputs from ADC. According to data sheet we need to pulse the RD 4 times in order to fetch. If I use the same very 10KHz clock source, then for pulsing RD , it will consume 4 clock cycles(min), then the data will be available to the control model only after 400us and not 100us. it is looking like a multi rate issue. I need to sample ADC with different clock(say 1 MHz) and make sure data is available to the control model every 100us. Is that correct?

 

[KlausST]

If I use the same very 10KHz clock source, then for pulsing RD

So you recognized this makes no sense. In no case.

So why not pulsing RD 4 (or more) times within the 100us?

There are two different things:
* Acquiring/sampling/converting ... is done with a fixed rate of 10kHz (100us)
* but you are free to read the conversion results with a different timing ... the only thing you have to care fore: Read the data before the new conversion results come in.

***

I need to sample ADC with different clock(say 1 MHz) and make sure data is available to the control model every 100us. Is that correct?

Makes no sense at all. I don´t understand.



Klaus

 

[curious_mind]

Ok I will put it this way. In my FPGA I have two logic blocks, one is ADC control logic block and another is the control algorithm. Both these blocks have clock as its inputs. Since my aim is synchronous design, I need to connect the same clock to both the models. So whatever clock I choose, I need to pulsate RD 4 or more times using this very clock. My control algorithm requires 4 analog data simultaneously to evaluate the output at any instance. Pulsing RD will require multiple clock cycle and the very definition that the entire model (ADC+Control algorithm) running on a single clock becomes invalid.

 

[FvM]

AD7606 can sample simultaneously up to 200 kS/s, of course also 100 or 10 kS/s. Just pulse CONVST periodically. A FPGA has nearly unlimited capabilities to utilize this data rate for your control system.

 

[curious_mind]

I could resolve this by using Rate transition block in simulink.