How to relate modules in Verilog ?

[test_out]

Verilog question!

Hi, im new in circuit designing. Now my project have some modules, and these module have relationship. So how can I relate them together?

Thanks

 

[jjww110]

Verilog question!

please connect them together using wire!!

 

[quan228228]

Re: Verilog question!

you should write a top file to combine sub-module files.

Regards
/David

 

[linuxluo]

Re: Verilog question!

hi,
find a verilog book and have a look, it's fundamental skill in design

 

[carrot]

Re: Verilog question!

Hi

Call all your submodules in your top module