How to reflect the effectiveness of STI(Shallow Trench Isolation) effect?

Hi,

For Layout dependent effect (LDE), the STI(Shallow Trench Isolation) is a big issue. If you do a simulation in advanced technology nodes, say, tsmc65nm or even 20nm, how can you tell whether you have reflected this STI in your simulation or what is the extend of SIT effect exposed in this simulation. I find there is no way to see if it is good or bad in terms of STI consideration in simulation until finally you have your design taped out and circuit manufactured. Then finally test of the real circuit may give you some clue. But even then, the reasons causing a chip not working are many. Any failure at this stage could not only be ascribed to STI. Anybody has any clue on how to reflect STI effect in a simulation? Your knowledge presented here would be highly appreciated.

Thanks,
Alex

Hi Alex,

Ya.I agree .STI is a big issue in recent techonology.But that is taken care by using the some standard simulation tool that also take care the stress effects in all the direction .For example "Litho electrical analyser".Hope by using this you can get some idea.

Thanks
Shrikant

shrikantbp said:

Hi Alex,

Ya.I agree .STI is a big issue in recent techonology.But that is taken care by using the some standard simulation tool that also take care the stress effects in all the direction .For example "Litho electrical analyser".Hope by using this you can get some idea.

Thanks
Shrikant

Click to expand...

Hi shrikant,,,.

Is this effect taken care in cadence virtuoso environment?.....

Thanks...

shrikantbp said:

Hi Alex,

But that is taken care by using the some standard simulation tool that also take care the stress effects in all the direction.

Click to expand...

Do you have any idea on how those tools taking care of STI if using Spectre or Spice simulator?

Regards,
Alex

Alex,

No.It is not taken care,We have to follow some guidelines which can reduce STI effect while working with layout.

Thanks
Shrikant