How to reduce the slack for reg2out?

[research235]

Dear all

I am working on timing ananlysis for the first time. after cts when i check for the setup timings i get the following values.


+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -4.082 | 0.000 | -0.615 | -4.082 | N/A | -0.559 |
| TNS (ns):| -1135.6 | 0.000 |-121.790 |-997.079 | N/A | -16.757 |
| Violating Paths:| 1107 | 0 | 552 | 468 | N/A | 87 |
| All Paths:| 42404 | 28604 | 16352 | 469 | N/A | 1685 |
+--------------------+---------+---------+---------+---------+---------+---------+

I see that the slack for reg2out is high . can some one please tell me how can I reduce. please provilde me some material to read inorder to solve this

Thank u in advance

 

[shelby]

reg2out

How are your IO pins constrained? If you could post a report + the IO constraint (set_output_delay) used it would be more helpful.

Off hand, I'm guessing it has to due with the clock skew between your internal clock and the external virtual clock used to constrain the IO pins. Check your reports to see what the difference is between launch clock and capture clock latency.

 

[vlsitechnology]

reg2out

Is it a block level project or a full chip?

 

[research235]

Re: reg2out

hello selby.

thank you for urreply the following a part of result form reg2out.tar file . can u throw soem light abt this . I see there is big slew for one cell . Any suggestion if this is the prob for high reg2out value

------------------------------------------------------+
| Cell | Slew | Delay | Arrival | Required |
| | | | Time | Time |
+----------------+-------+-------+---------+----------|
| | 0.300 | | 1.000 | -5.609 |
| CKLNQD8 | 0.300 | 0.000 | 1.000 | -5.609 |
| SDFCNXD | 0.032 | 0.220 | 1.220 | -5.389 |
| | | | | |
| CKND2 | 0.031 | 0.031 | 1.251 | -5.358 |
| | | | | |
| CKND2D | 0.044 | 0.038 | 1.289 | -5.320 |
| | | | | |
| NR2XD | 0.086 | 0.074 | 1.363 | -5.246 |
| | | | | |
| CKND2B | 0.029 | 0.042 | 1.405 | -5.204 |
| | | | | |
| TPND3D | 0.069 | 0.045 | 1.450 | -5.159 |
| | | | | |
| INVD16B | 0.026 | 0.034 | 1.485 | -5.125 |
| INVD18B | 5.686 | 3.020 | 4.505 | -2.105 |
| | 8.886 | 3.793 | 8.297 | 1.688 |
------------------------------------------------------+