How to reduce the Radiation in Microstrip (Top layer) ??

[kabaleevisu]

Hi everyone,
In my Board DDR3 section has some issue,Let me anyone give the solution.
DDR clock (Clk_0 & CLK#_0).Routed in top layer(Microstrip) because due to the less number of layer count.(Board has Eight layers)Four 4 DDR section used so, 64 Data signal occupied in two inner layer and Remaining layer for reference plane.Address and Clock are routed in Mictro strip only .I got feedback from SI team,Clock signal need to route in inner layer for avoiding radiation but if i followed those SI input, I need to increase the layer for clock signal for reference as well as clock signal has affect the enter path of data signal and I could not increase the layer count. I need to fix the problem so any one suggest the valuable solution to avoid the radiation in Top layer.

 

[jiripolivka]

There is a basic rule for a microstrip to reduce radiation: do not insert any inhomogeneity to it like bends and components.
Otherwise it must radiate. You can add a metal screen above the line or make a symmetrical microstrip.

 

[marce]

The most likely signal that will radiate and cause EMC problems is the clock, try and get it on an inner layer....

 

[mtwieg]

Is it a differential clock? If so you can decrease the spacing between the traces and decrease the dielectric thickness. Definitely not as effective as using an inner layer though.

 

[D.A.(Tony)Stewart]

I get low cross talk on balanced microstrip using interleaved grounds between pairs.
-140dB on 12 port T1 distribution layout @1.544Mhz

 

[kabaleevisu]

Hi,
Thanks for your valuable comments. Let me explain any one should I route the clock signal in between data Group (byte).if I route between the group will it be a signal integrity issue.(cross talk, radiation) ??

 

[criterion456]

Hi everyone,
In my Board DDR3 section has some issue,Let me anyone give the solution.
DDR clock (Clk_0 & CLK#_0).Routed in top layer(Microstrip) because due to the less number of layer count.(Board has Eight layers)Four 4 DDR section used so, 64 Data signal occupied in two inner layer and Remaining layer for reference plane.Address and Clock are routed in Mictro strip only .I got feedback from SI team,Clock signal need to route in inner layer for avoiding radiation but if i followed those SI input, I need to increase the layer for clock signal for reference as well as clock signal has affect the enter path of data signal and I could not increase the layer count. I need to fix the problem so any one suggest the valuable solution to avoid the radiation in Top layer.

There are some basic rules :


1. Avoid sharp bends :





2. GND Fill




3. stitching GND vias




4. large and complete GND plane




5. Make sure the GND plane underneath the signal is complete, ,not broken




6. Stripline (inner layer) instead of microstrip line


7. Avoid fringing effect by 20H rule