How to reduce the phase noise of a ring VCO

[knights]

reduce phase noise

Hi guys,

I am designing a ring VCO. When I do the phase noise simulation. I found the phase noise is not good and main contribution of phase noise is come from the
bias current, that is to say, the opamp in bandgap.

How can I filter the bias noise? I know that add a external big cap can filter this and the simulation verify this method .But actually I can not get an extra pad to do this. Any other suggestion?

Any input is appreciated.

 

[dick_freebird]

self biased vco + reducing phase noise

You probably want your bias to be "stiff" at the point of
use (the current mirrors) and decoupled from the BG/
OA noises. A RC filter might be adequate, high-Q caps
will at least kill the higher frequency noise.

You would like to minimize bias kV so that bias noise
has less of a contribution. Excess tuning range worsens
phase noise.

In addition to your bias-path noise you would like to
have a look at supply noise, self-generated noise and
effects like rail-span collapse (inside the package L
and layout R losses) can flatten inverter gain in-the-
moment, lower gain makes greater phase perturbation
per voltage.

Current starving may degrade gain while it degrades
(on purpose) drive. At low operating frequencies you
might prefer to have a composite inverter with high
gain and only a variable output current (say, starve
only the third inverter of a trio chain, each trio being
one "inverter". Or you might prefer unstarved inverter
and a RC lag network with the capacitor being a MOS
varactor. Switches have minimum MOS noise, resistors
are as good as it gets, and the cap bias you can filter
the heck out of. But current mirror MOS are pretty bad
noise actors and in a simple ring design they are direct
to the output.

 

[knights]

Current starving may degrade gain while it degrades
(on purpose) drive. At low operating frequencies you
might prefer to have a composite inverter with high
gain and only a variable output current (say, starve
only the third inverter of a trio chain, each trio being
one "inverter". Or you might prefer unstarved inverter
and a RC lag network with the capacitor being a MOS
varactor. Switches have minimum MOS noise, resistors
are as good as it gets, and the cap bias you can filter
the heck out of. But current mirror MOS are pretty bad
noise actors and in a simple ring design they are direct
to the output.

Thanks for your inputs. Yes , for a simple ring design, current mirror MOS are pretty bad noise actors. I am looking forward to reduce the influnce.

 

[knights]

Any suggestion?

 

[mmic1978]

Current mirror bias maybe degrad PN about 10dB

Use large L and design more overdrive voltage for current mirror bias

 

[saro_k_82]

You might also try filtering the VGS voltage just before the main current output. Since this filter comes in between two gates, you can have a large resistance (which is obtained from MOS channel to save area) and a cap that you could live with.

 

[ozgura2]

Use a high poly resistor + capacitor low pass filter to filter low frequency noise. For example 1Mega ohm resistor plus 100pF MOS capacitor.