How to reduce the open loop gain of the last stage including Pass Tr (like using a small length) of LDO?

[dressler6]

Hello Friends Im new to the whole Power Management and Analog Design sphere .
I have a question. If anyone knows, please tell me.

As a general LDO, the output PASS Tr. is PMOS.
To improve PSR+, the open loop gain of PASS Tr can be reduced. How to reduce the open loop gain of the last stage including Pass Tr (like using a small length) of LDO?

 

[dick_freebird]

You could make the final / pass stage a current mirror (high but not as high gain as a common source gain stage). You might want some more care with the gate drive of that fat little beast.

 

[dressler6]

You could make the final / pass stage a current mirror (high but not as high gain as a common source gain stage). You might want some more care with the gate drive of that fat little beast.

That's good point!! Thank you very much.

I will look for related papers and think about ways to improve PSR+.