How to reduce the leak current in sleep mode

Status
Not open for further replies.
W

wkong_zhu

Full Member level 3
Joined
Nov 13, 2004
Messages
174
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,296
Activity points
1,293
When the chip is in sleep mode, all digital part has no clock, but the chip has >100uA leak current, Why? how can I find the leak source, and how to reduce it?
 

Leakage is a physical feature of small geometris

You can not do anything about it on design level, You have to change
type of transistors to for instance HighVt transistors

or turn that part off, i.e. no VDD => no leakage

/Konrad
 

wkong_zhu said:
When the chip is in sleep mode, all digital part has no clock, but the chip has >100uA leak current, Why? how can I find the leak source, and how to reduce it?
Click to expand...

That isn't leakage - something is still turned on. Follow eXnol's suggestions.

Keith.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…