How to reduce the DC offset for the op amp?

[twinkle81]

I have an op amp design. Vdd = 1.2V, Vss = 0V. The output shows a DC offset of
-0.3mV. When i increase my Vss to -1.2V, the offset increases to -100mV at the output.

I was wondering what causes this offset and how can i remove it.

 

[instruite]

Which opamp are you using??

Some opamps have offset compensation pins also

 

[Humungus]

What it actually matters is the input-referred offset. Offset actually depends on the common mode input voltage. When you say that your initial offset is -0.3mV, respect to what? Is it input- or output-referred? What input voltage? What's the configuration you use to determine the offset? Is your input voltage within the valid common mode range? Are you talking about systematic or random offset? Systematic offset depends on your design and bias conditions. Random offset depends on transistor mismatch, which in turns depends on transistors sizes and bias. Analize all this and calculate what is your spected offset.

To see the result of the random offset, you need to perform Monte Carlo simulations? Do tou have a proper mismatch model? Do you simulate in all posible corners?

 

[sunking]

it seems that the input stage is triode state. The offset should not be so large.
check the Operation points

 

[tsanlee]

I have an op amp design. Vdd = 1.2V, Vss = 0V. The output shows a DC offset of
-0.3mV. When i increase my Vss to -1.2V, the offset increases to -100mV at the output.

I was wondering what causes this offset and how can i remove it.

In your application,the application voltage induce offset to your OPA,
You can check these item:

1.input common mode range
2.the device mismatch (channel length modulation effect),let current miror failure.
3.VDD=1.2V ,what process do you have? 1.2v VDD is in OPA application voltage range.

 

[SkyHigh]

twinkle81,

It would be very useful if you upload your circuit here for everyone to spot problems in your circuit.

 

[twinkle81]

Well the op amp is custom made by my seniors and I'm suppose to fine tune his design.

The offset i think would be systematic offset with respect to ground. I tried making the DC supply positive side small around 0.5V. The offset seem to turn positive instead of the -ve like what I got when i set both supplies at 1.2 and -1.2 V.

I'm using mentor graphics to simulate all these, still quite new to it. Haha. Exploring the Monte Carlo function still like what Humungus have mentioned.

I dun think it will be device mismatched because i'm using identical devices in the simulator for the current mirrors.

Let me find out how to upload the circuit in this forum...

 

[instruite]

twinkle81 wrote:

Let me find out how to upload the circuit in this forum...

Save your circuit as image file (you can also do using printscreen and then editing image in paint)
and while you are replying to post or adding a post there is Add an Attachment section where you can just browse for the file path on your local system and Press Add Attachment button

 

[twinkle81]

Thanks alot instruite! But now the problem is i do not know how to take the circuit out from Mentor Graphics schematic and put it as a file into this forum.

Any mentor graphic experts around to help??

 

[hardings]

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