how to reduce jitter from a video stream?

Status
Not open for further replies.
H

hamidkavianathar

Member level 5
Joined
Mar 6, 2016
Messages
89
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
804
Hi guys
I am working on a project with fpga (spartan 6 xc6slx9 tqg144). my input is parallel video stream. it consist of 8 bits data and a 27 MHz clock signal. I want to store 4 frames of video and then read it with another 27 MHz clock signal. it is shown in below image.



as these clocks are not the same clock sometimes I should read a frame twice and some times I should overwrite a frame. my problem is that the output image has a lot of jitter.
although my is design is very small and it does not span a lot of fpga resource, it does not work properly. for example when I add chipscope to my design it shows some unrelated data. I am totally confused. I don't know what I am missing. could anyone tell me what I should do?
thanks.
here is my ucf file and verilog code.

the top.v file:
Code: 
`timescale 1ns / 1ps
`default_nettype none

module top(


			
	output wire [7:0] data_out_sdi,
	output wire clk_out_sdi,
	
	input wire [7:0] data_in_sdi_c,
	input  wire clk_in_sdi_in,
	
	input wire clk_in,
	
	//output wire [3:0] led,
	input wire reset, // active low
	// SDRAM
	
	output wire SDRAM_CLK,
	output wire SDRAM_CKE,
	output wire SDRAM_WEn,
	output wire SDRAM_CASn,
	output wire SDRAM_RASn,
	output wire SDRAM_CSn,
	output wire [12:0] SDRAM_A,
	output wire [1:0] SDRAM_BA,
	output wire [1:0] SDRAM_DQM,
	inout wire [15:0] SDRAM_DQ);

 
localparam [2:0] idle = 3'h4;
localparam [2:0] write = 3'h1;
localparam [2:0] read = 3'h2;
localparam [2:0] write_into_memory = 3'h3;
localparam [2:0] wait_for_fifo_in = 3'h0;
localparam [2:0] write_1 = 3'h5;
localparam [2:0] read_1 = 3'h6;


localparam state_wait_for_trs = 0;
localparam state_trs_found = 1;




reg RdReq;
wire WrGnt;
wire RdGnt;
wire RdDataValid;
reg WrReq;


wire clk_140;
wire clk_140_inv;


reg next_state_top;
reg current_state_top;

reg [2:0] next_state_controller;
reg [2:0] current_state_controller;

reg reset_active_high;
reg reset_active_high1;

reg reset_27_meg1;
reg reset_27_meg2;

wire start_of_frame_detected;

reg [7:0] data_in_sdi_r1;
reg [7:0] data_in_sdi_r2;
reg [7:0] data_in_sdi_r3;
reg [7:0] data_in_sdi_r4;
reg [7:0] data_in_sdi_r5;
reg [7:0] data_in_sdi_r6;

wire [15:0] dout_fifo_in;
wire wr_en_fifo_in;
reg rd_en_fifo_in;	
wire valid_fifo_in;
wire prog_empty_fifo_in;

wire [15:0] RdData;
wire clk_in_sdi;
reg [15:0] dout_fifo_in_reg;
reg [6:0] count_read;
reg [6:0] count_write;


wire valid;
wire clk_27_out;
wire full_fif0o_out;
wire empty_fifo_out;
wire [7:0] dout_fifo_out;
wire clk_27_out_inv;
wire prog_full_fifo_out;

reg rst_count_read;
reg rst_count_write;

reg [24:0] read_address_0;
reg [24:0] write_address_0;
wire [24:0] write_address;
wire [24:0] read_address;


wire frame_write_finished;
wire [24:0] address_start_read;
wire [24:0] address_start_write;
reg [1:0] frame_select_rd;
reg [1:0] frame_select_wr;
wire frame_read_finished;

//reg en_write_address;
reg rst_write_address;

//reg en_read_address;
reg rst_read_address;

ODDR2 #(
  .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
  .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
  .SRTYPE("ASYNC") // Specifies "SYNC" or "ASYNC" set/reset
) clk_out_27 (
  .Q(clk_out_sdi),     // 1-bit DDR output data
  .C0(clk_27_out),  // 1-bit clock input
  .C1(clk_27_out_inv), // 1-bit clock input
  .CE(1'b1),      // 1-bit clock enable input
  .D0(1'b0), // 1-bit data input (associated with C0)
  .D1(1'b1), // 1-bit data input (associated with C1)
  .R(1'b0),   // 1-bit reset input
  .S(1'b0)   // 1-bit set input
);





ODDR2 #(
  .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
  .INIT(1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
  .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) memory_105 (
  .Q(SDRAM_CLK),     // 1-bit DDR output data
  .C0(clk_140),  // 1-bit clock input
  .C1(clk_140_inv), // 1-bit clock input
  .CE(1'b1),      // 1-bit clock enable input
  .D0(1'b0), // 1-bit data input (associated with C0)
  .D1(1'b1), // 1-bit data input (associated with C1)
  .R(1'b0),   // 1-bit reset input
  .S(1'b0)   // 1-bit set input
);



SDRAM_ctrl sdram_controller(
    .clk(clk_140), 
    .RdReq(RdReq), 
    .RdGnt(RdGnt), 
    .RdAddr(read_address_0), 
    .RdData(RdData), 
    .RdDataValid(RdDataValid), 
    .WrReq(WrReq), 
    .WrGnt(WrGnt), 
    .WrAddr(write_address_0), 
    .WrData(dout_fifo_in), 
    .SDRAM_CKE(SDRAM_CKE), 
    .SDRAM_WEn(SDRAM_WEn), 
    .SDRAM_CASn(SDRAM_CASn), 
    .SDRAM_RASn(SDRAM_RASn), 
    .SDRAM_CSn(SDRAM_CSn), 
    .SDRAM_A(SDRAM_A), 
    .SDRAM_BA(SDRAM_BA), 
    .SDRAM_DQM(SDRAM_DQM), 
    .SDRAM_DQ(SDRAM_DQ)
    );



fifo_in fifo_i (
  .rst(reset_active_high), // input rst
  .wr_clk(clk_in_sdi), // input wr_clk
  .rd_clk(clk_140), // input rd_clk
  .din(data_in_sdi_r6), // input [7 : 0] din
  .wr_en(wr_en_fifo_in), // input wr_en
  .rd_en(rd_en_fifo_in), // input rd_en
  .dout(dout_fifo_in), // output [15 : 0] dout
  .full(), // output full
  .empty(), // output empty
  .valid(valid_fifo_in), // output valid
  .prog_empty(prog_empty_fifo_in) // output prog_empty
);


wire valid_fifo_out;

fifo_o fifo_out (
  .rst(reset_active_high), // input rst
// .rst(reset_active_high), // input rst 
  .wr_clk(clk_140), // input wr_clk
  .rd_clk(clk_27_out), // input rd_clk
  .din(RdData), // input [15 : 0] din
  .wr_en(RdDataValid), // input wr_en
  .rd_en(1'b1), // input rd_en
  .dout(dout_fifo_out), // output [7 : 0] dout
  .full(), // output full
  .empty(), // output empty
  .valid(valid_fifo_out), // output valid
  .prog_full(prog_full_fifo_out) // output prog_full
);

trs_detector start_of_frame_detector (
    .clk(clk_in_sdi), 
    .rst(reset_27_meg2), 
    .data_in(data_in_sdi_r1), 
    .start_of_frame_detected(start_of_frame_detected)
    );


dcm clock_wizard(// Clock in ports
	.CLK_IN1(clk_in),      // IN
	// Clock out ports
	.CLK_OUT1(clk_140),     // OUT
	.CLK_OUT2(clk_140_inv),     // OUT
    .CLK_OUT3(clk_27_out),    // OUT
	.CLK_OUT4(clk_27_out_inv));      // OUT

//assign clk_in_sdi = clk_in_sdi_in;
	
dcm2 clock_wizard2(// Clock in ports
    .CLK_IN1(clk_in_sdi_in),      // IN
    // Clock out ports
    .CLK_OUT1(clk_in_sdi));    // OUT
	
	
assign data_out_sdi = dout_fifo_out;


	
always @( posedge clk_140) begin
	reset_active_high1 <= reset;
	reset_active_high <= reset_active_high1;
end


always @( posedge clk_in_sdi) begin
	reset_27_meg1 <= reset_active_high;
	reset_27_meg2 <= reset_27_meg1;
end



always @( posedge clk_in_sdi) begin
	data_in_sdi_r1 <= data_in_sdi_c;
	data_in_sdi_r2 <= data_in_sdi_r1;
	data_in_sdi_r3 <= data_in_sdi_r2;
	data_in_sdi_r4 <= data_in_sdi_r3;
	data_in_sdi_r5 <= data_in_sdi_r4;
	data_in_sdi_r6 <= data_in_sdi_r5;
	
end






always @( posedge clk_in_sdi) begin
	if (reset_27_meg2 == 1'b1)
		current_state_top <= state_wait_for_trs;
	else
		current_state_top <= next_state_top;
end

always @* begin
	case (current_state_top)
		state_wait_for_trs: begin
			if (start_of_frame_detected == 1'b1)
				next_state_top = state_trs_found;
			else
				next_state_top = state_wait_for_trs;
				
			end
		state_trs_found: 
				next_state_top = state_trs_found;

	endcase
end

assign wr_en_fifo_in = (current_state_top == state_trs_found) ? 1'b1: 1'b0;

assign address_start_read = ((frame_select_rd == 2'b00) ? 25'h0000000:
							((frame_select_rd == 2'b01) ? 25'h0800000:
							((frame_select_rd == 2'b10) ? 25'h1000000:
							((frame_select_rd == 2'b10) ? 25'h1800000: 25'h1800000))));

							
assign address_start_write = ((frame_select_wr == 2'b00) ? 25'h0000000:
							 ((frame_select_wr == 2'b01) ? 25'h0800000:
							 ((frame_select_wr == 2'b10) ? 25'h1000000:
							 ((frame_select_wr == 2'b10) ? 25'h1800000: 25'h1800000))));



always @( posedge clk_140) begin
	if ((reset_active_high == 1'b1) || (rst_read_address == 1'b1))
		read_address_0 <= 0;
	else if (RdGnt == 1'b1)
		read_address_0 <= read_address_0 + 1'b1;
	else
		read_address_0 <= read_address_0;
end

assign read_address = read_address_0 + address_start_read;

assign frame_read_finished = (read_address_0 == 25'h0107ABE) ? 1'b1: 1'b0;

always @( posedge clk_140) begin
	if ((reset_active_high == 1'b1) || (rst_write_address == 1'b1))
		write_address_0 <= 0;
	else if (valid_fifo_in == 1'b1)
		write_address_0 <= write_address_0 + 1'b1;
	else
		write_address_0 <= write_address_0;
end

assign write_address = write_address_0 + address_start_write;

assign frame_write_finished = (write_address_0 == 25'h0107ABE) ? 1'b1: 1'b0;


always @( posedge clk_140) begin
	if (reset_active_high == 1'b1) begin
		frame_select_rd <= 2'h2;
		rst_read_address <= 1'b1;
		end
		
	else if (frame_read_finished == 1'b1) begin
		rst_read_address <= 1'b1;
		if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h0)) begin
				frame_select_rd <= 2'h0;	//don't care
			end
		else if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h1)) begin
				frame_select_rd <= 2'h2;
			end
		else if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h2)) begin
				frame_select_rd <= 2'h3;
			end
		else if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h3)) begin
				frame_select_rd <= 2'h3;
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h0)) begin
				frame_select_rd <= 2'h0;
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h1)) begin
				frame_select_rd <= 2'h1;	//don't care
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h2)) begin
				frame_select_rd <= 2'h3;
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h3)) begin
				frame_select_rd <= 2'h0;
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h0)) begin
				frame_select_rd <= 2'h1;
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h1)) begin
				frame_select_rd <= 2'h1;
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h2)) begin
				frame_select_rd <= 2'h2;	//don't care
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h3)) begin
				frame_select_rd <= 2'h0;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h0)) begin
				frame_select_rd <= 2'h1;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h1)) begin
				frame_select_rd <= 2'h2;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h2)) begin
				frame_select_rd <= 2'h2;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h3)) begin
				frame_select_rd <= 2'h3;		//don't care
			end	
		else 
			frame_select_rd <= 2'h0;
	end
	else begin
		frame_select_rd <= frame_select_rd;
		rst_read_address <= 1'b0;
		end
end


always @( posedge clk_140) begin
	if (reset_active_high == 1'b1) begin
		frame_select_wr <= 2'h0;
		rst_write_address <= 1'b1;
		end
	else if (frame_write_finished == 1'b1) begin
		rst_write_address <= 1'b1;
		if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h0)) begin
				frame_select_wr <= 2'h0;	//don't care
			end
		else if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h1)) begin
				frame_select_wr <= 2'h0;
			end
		else if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h2)) begin
				frame_select_wr <= 2'h1;
			end
		else if ((frame_select_wr == 2'h0) && (frame_select_rd == 2'h3)) begin
				frame_select_wr <= 2'h1;
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h0)) begin
				frame_select_wr <= 2'h2;
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h1)) begin
				frame_select_wr <= 2'h1;	//don't care
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h2)) begin
				frame_select_wr <= 2'h1;
			end
		else if ((frame_select_wr == 2'h1) && (frame_select_rd == 2'h3)) begin
				frame_select_wr <= 2'h2;
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h0)) begin
				frame_select_wr <= 2'h3;
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h1)) begin
				frame_select_wr <= 2'h3;
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h2)) begin
				frame_select_wr <= 2'h2;	//don't care
			end
		else if ((frame_select_wr == 2'h2) && (frame_select_rd == 2'h3)) begin
				frame_select_wr <= 2'h2;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h0)) begin
				frame_select_wr <= 2'h3;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h1)) begin
				frame_select_wr <= 2'h0;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h2)) begin
				frame_select_wr <= 2'h0;
			end
		else if ((frame_select_wr == 2'h3) && (frame_select_rd == 2'h3)) begin
				frame_select_wr <= 2'h3;		//don't care
			end			
		else
			frame_select_wr <= 2'h3;
		end
	else begin
		frame_select_wr <= frame_select_wr;
		rst_write_address <= 1'b0;
		end
end
	

always @(posedge clk_140) begin
	if (rst_count_write == 1'b1)
		count_write <= 0;
	else if (valid_fifo_in == 1'b1) 
		count_write <= count_write + 1'b1;
	else
		count_write <= count_write;
end

always @(posedge clk_140) begin
	if (rst_count_read == 1'b1)
		count_read <= 0;
	else if (RdGnt == 1'b1)
		count_read <= count_read + 1'b1;
	else
		count_read <= count_read;
end

always @(posedge clk_140) begin
	if (reset_active_high == 1'b1)
		current_state_controller <= wait_for_fifo_in;
	else
		current_state_controller <= next_state_controller;
end


//assign rd_en_fifo_in = (current_state_controller == write) ? 1'b1: 1'b0;

always @* begin
	case (current_state_controller)
	
		wait_for_fifo_in: begin
				rst_count_read = 1'b1;
				rst_count_write = 1'b1;
				rd_en_fifo_in = 1'b0;

			if (prog_empty_fifo_in != 1'b1) begin
				next_state_controller = write_1;
				WrReq = 1'b1;
				RdReq = 1'b0;
				end
			else begin
				next_state_controller = wait_for_fifo_in;
				WrReq = 1'b0;
				RdReq = 1'b0;
				end
			end
		idle: begin
				rst_count_read = 1'b1;
				rst_count_write = 1'b1;
				rd_en_fifo_in = 1'b0;
			if (prog_empty_fifo_in != 1'b1) begin
				next_state_controller = write_1;
				WrReq = 1'b1;
				RdReq = 1'b0;
				end
			else if (prog_full_fifo_out != 1'b1) begin
				next_state_controller = read_1;
				WrReq = 1'b0;
				RdReq = 1'b1;
				end
			else begin
				next_state_controller = idle;
				WrReq = 1'b0;
				RdReq = 1'b0;
				end
			end

		write_1: begin
				rst_count_read = 1'b1;
				rst_count_write = 1'b1;
				WrReq = 1'b1;
				RdReq = 1'b0;
				rd_en_fifo_in = 1'b0;
				if (WrGnt == 1'b1) 
					next_state_controller = write;
				else
					next_state_controller = write_1;

				end
			
		write: begin
				rst_count_read = 1'b1;
				if (count_write >= 25'h20) begin
					next_state_controller = idle;
					rst_count_write = 1'b1;
					WrReq = 1'b0;
					RdReq = 1'b0;
					rd_en_fifo_in = 1'b0;
					end
				else begin
					next_state_controller = write;
					rst_count_write = 1'b0;
					WrReq = 1'b1;
					RdReq = 1'b0;
					rd_en_fifo_in = 1'b1;
					end
					
				end
		read_1: begin
				WrReq = 1'b0;
				rd_en_fifo_in = 1'b0;
				rst_count_write = 1'b1;
				if (RdGnt == 1'b1) begin
					next_state_controller = read;
					rst_count_read = 1'b0;
					RdReq = 1'b1;
					end
				else begin
					next_state_controller = read_1;
					rst_count_read = 1'b0;
					RdReq = 1'b1;
					end
					

			end

		read: begin
				WrReq = 1'b0;
				rst_count_write = 1'b1;
				rd_en_fifo_in = 1'b0;
				if (count_read >= 25'h20) begin
					next_state_controller = idle;
					rst_count_read = 1'b1;
					RdReq = 1'b0;
					end
				else begin
					next_state_controller = read;
					rst_count_read = 1'b0;
					RdReq = 1'b1;
					end
					

			end
		

		default: begin
				WrReq = 1'b0;
				RdReq = 1'b0;
				rd_en_fifo_in = 1'b0;
				next_state_controller = idle;
				rst_count_read = 1'b1;
				rst_count_write = 1'b1;
			end
			
	endcase

end



endmodule

and this my ucf file:
Code: 
NET "clk_in" LOC = P55;
NET "clk_in" IOSTANDARD = LVCMOS33;


NET "clk_in_sdi_in" LOC = P93;
NET "data_in_sdi_c[0]" LOC = P102;
NET "data_in_sdi_c[1]" LOC = P101;
NET "data_in_sdi_c[2]" LOC = P100;
NET "data_in_sdi_c[3]" LOC = P99;
NET "data_in_sdi_c[4]" LOC = P98;
NET "data_in_sdi_c[5]" LOC = P97;
NET "data_in_sdi_c[6]" LOC = P95;
NET "data_in_sdi_c[7]" LOC = P94;

NET "clk_in_sdi_in" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[7]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[6]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[5]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[4]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[3]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[2]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[1]" IOSTANDARD = LVCMOS33;
NET "data_in_sdi_c[0]" IOSTANDARD = LVCMOS33;



NET "clk_out_sdi" LOC = P50;
NET "data_out_sdi[0]" LOC = P5;
NET "data_out_sdi[1]" LOC = P6;
NET "data_out_sdi[2]" LOC = P7;
NET "data_out_sdi[3]" LOC = P8;
NET "data_out_sdi[4]" LOC = P9;
NET "data_out_sdi[5]" LOC = P10;
NET "data_out_sdi[6]" LOC = P11;
NET "data_out_sdi[7]" LOC = P12;


NET "SDRAM_A[0]" LOC = P78;
NET "SDRAM_A[1]" LOC = P115;
NET "SDRAM_A[2]" LOC = P117;
NET "SDRAM_A[3]" LOC = P116;
NET "SDRAM_A[4]" LOC = P105;
NET "SDRAM_A[5]" LOC = P88;
NET "SDRAM_A[6]" LOC = P87;
NET "SDRAM_A[7]" LOC = P85;
NET "SDRAM_A[8]" LOC = P84;
NET "SDRAM_A[9]" LOC = P83;
NET "SDRAM_A[10]" LOC = P79;
NET "SDRAM_A[11]" LOC = P82;
NET "SDRAM_A[12]" LOC = P81;

NET "SDRAM_CASn" LOC = P22;

NET "SDRAM_CKE" LOC = P111;

NET "SDRAM_CLK" LOC = P132;

NET "SDRAM_CSn" LOC = P24;

NET "SDRAM_DQ[0]" LOC = P142;
NET "SDRAM_DQ[1]" LOC = P141;
NET "SDRAM_DQ[2]" LOC = P140;
NET "SDRAM_DQ[3]" LOC = P139;
NET "SDRAM_DQ[4]" LOC = P138;
NET "SDRAM_DQ[5]" LOC = P137;
NET "SDRAM_DQ[6]" LOC = P134;
NET "SDRAM_DQ[7]" LOC = P133;
NET "SDRAM_DQ[8]" LOC = P131;
NET "SDRAM_DQ[9]" LOC = P127;
NET "SDRAM_DQ[10]" LOC = P126;
NET "SDRAM_DQ[11]" LOC = P124;
NET "SDRAM_DQ[12]" LOC = P123;
NET "SDRAM_DQ[13]" LOC = P121;
NET "SDRAM_DQ[14]" LOC = P119;
NET "SDRAM_DQ[15]" LOC = P118;
NET "SDRAM_DQM[0]" LOC = P30;
NET "SDRAM_DQM[1]" LOC = P32;
NET "SDRAM_RASn" LOC = P23;
NET "SDRAM_WEn" LOC = P21;



NET "SDRAM_A[0]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[1]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[2]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[3]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[4]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[5]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[6]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[7]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[8]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[9]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[10]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[11]" IOSTANDARD = LVCMOS33;
NET "SDRAM_A[12]" IOSTANDARD = LVCMOS33;
NET "SDRAM_BA[0]" IOSTANDARD = LVCMOS33;
NET "SDRAM_BA[1]" IOSTANDARD = LVCMOS33;
NET "SDRAM_CASn" IOSTANDARD = LVCMOS33;
NET "SDRAM_CKE" IOSTANDARD = LVCMOS33;
NET "SDRAM_CLK" IOSTANDARD = LVCMOS33;
NET "SDRAM_CSn" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[0]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[1]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[2]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[3]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[4]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[5]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[6]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[7]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[8]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[9]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[10]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[11]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[12]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[13]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[14]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQ[15]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQM[0]" IOSTANDARD = LVCMOS33;
NET "SDRAM_DQM[1]" IOSTANDARD = LVCMOS33;
NET "SDRAM_RASn" IOSTANDARD = LVCMOS33;
NET "SDRAM_WEn" IOSTANDARD = LVCMOS33;



NET "SDRAM_BA[0]" LOC = P26;
NET "SDRAM_BA[1]" LOC = P27;

NET "reset" LOC = P35;

NET "reset" IOSTANDARD = LVCMOS33;


# PlanAhead Generated IO constraints 
NET "data_out_sdi[7]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[6]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[5]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[4]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[3]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[2]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[1]" IOSTANDARD = LVCMOS33;
NET "data_out_sdi[0]" IOSTANDARD = LVCMOS33;
NET "clk_out_sdi" IOSTANDARD = LVCMOS33;

#Created by Constraints Editor (xc6slx9-tqg144-3) - 2017/05/03
NET "clk_in" TNM_NET = clk_in;
TIMESPEC TS_clk_in = PERIOD "clk_in" 20 ns HIGH 50%;

NET "clk_in_sdi_in" TNM_NET = clk_in_sdi_in;
TIMESPEC TS_clk_in_sdi_in = PERIOD "clk_in_sdi_in" 37.037 ns HIGH 50%;

NET "clk_in_sdi" TNM_NET = clk_in_sdi;
TIMESPEC TS_clk_in_sdi = PERIOD "clk_in_sdi" 37.037 ns HIGH 50%;

NET "clk_140" TNM_NET = clk_140;
TIMESPEC TS_clk_140 = PERIOD "clk_140" 13.333 ns HIGH 50%;

NET "clk_27_out" TNM_NET = clk_27_out;
TIMESPEC TS_clk_27_out = PERIOD "clk_27_out" 37.037 ns HIGH 50%;



TIMESPEC "TS_CDC_1" = FROM "clk_140" TO "clk_in_sdi" TIG;
#TIMESPEC "TS_CDC_1" = FROM "clk_140" TO "clk_27_out" TIG;
#TIMESPEC "TS_CDC_1" = FROM "clk_in_sdi" TO "clk_27_out" TIG;


#PIN "clock_wizard/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;

I apologize for my bad English.
 

adding or deleting entire frames of data will cause video to jitter a lot, that is enough data loss (added) to result in highly visible issues. MPEG use things like PCR to keep the destination clock frequency locked with the source. A PLL is locked to the PCR counter and the PLL frequency is adjusted based on the drift between the incoming PCR in the stream and the local PCR counter.

Seriously the whole approach you are taking will not work well for smooth video.
 
thanks for the comment. I will consider them. I don't know why chipscope does not work for me, for example I have used a counter to count the number of writes or reads from memory, but when I am using a chipscope to watch the value of the counter I see some unrelated and random numbers. I don't know what I am missing.
 

One thing I've noticed is you've got constraints added for the input and output of the DCMs. This is wrong, you should only supply the constraint to the input o the DCM. see this thread on Xilinx's forum. By adding the constraints to both the input and outputs of the DCM you've basically told the tools to ignore all the paths between the clocks.

The randomness may be due to an asynchronous reading of the counters. The design from what I gather uses different clocks for the reading and writing of the SDRAM so if you chipscope the wrong place and use a clock that is asynchronous to one or both domains you'll never reliably capture data.
 

Sounds like timing problems. Are you sampling the counter with the correct clock? is all the logic clocked in the correct clock domains? have you done safe CDC?
 
- - - Updated - - -

TrickyDicky said:
Sounds like timing problems. Are you sampling the counter with the correct clock? is all the logic clocked in the correct clock domains? have you done safe CDC?
Click to expand...

thanks for the comment. I am sure that I have not used any signal from one clock domain in another clock domain. I have put a fifo between two clock domain. I don't know what I am missing.
I apologize for answering late.

- - - Updated - - -


thanks for the comment. I remove that constraint but the chipscope is still showing incorrect data. I have used the "clk_140" clock for reading from and writing into memory. I have used the "clk_140" clock between two FIFOs including SDRAM controller. reading and writing from memory and fifos are synchronous. I have three clock domain, between clock domains, I have used a FIFO. I think I have considered all of the rules. could you please tell me, what I should do? which constraints should I use in my ucf file? thanks you very much.
I apologize for answering late.
 

It's very difficult without specifics to determine what may be wrong (as there could be many things that cause such problems). Both TrickyDicky and I have touched on the two most major ones that usually cause problems. Without a look at the design it may be very difficult to determine the root cause of the problem.

It could be that chipscope is telling you the truth and you have an issue in the design that gives you incorrect data.
 

Thanks for the comnent. I am sure that chipscope is showing wrong data, because when I remove some parts of my design, it shows valid data. I am totally confused.

- - - Updated - - -

Could you please tell me some reasons that may cause this problem?
 


Hmm,
1) How packed is the design and what options are you using for implementation?
2) What does the timing report say about unconstrained paths?
 

What makes you so sure that Chipscope is wrong? You removed part of the design and it "worked"; then you put parts back in and then it didn't "work". What if the part you took out was what was messing up your data?
 
I'm assuming this clk140 constraint was removed. The UCF had it at 75MHz, which could be correct, but probably not.

If removing unrelated logic causes the design to work, I would be suspicious of timing constraints.
 
ads-ee said:
Hmm,
1) How packed is the design and what options are you using for implementation?
2) What does the timing report say about unconstrained paths?
Click to expand...

thanks for the reply.
these are my synthesis and implementation option:

and

and

and












- - - Updated - - -

barry said:
What makes you so sure that Chipscope is wrong? You removed part of the design and it "worked"; then you put parts back in and then it didn't "work". What if the part you took out was what was messing up your data?
Click to expand...

thanks for your attention. in these images I have showed the input video stream. in first image I can see the input data very well but in the second the chipscope shows invalid data. for example in the second image the trigger value is 0xFF but in waveform it shows 0x07 instead of 0xFF. I apologize for my bad English.



- - - Updated - - -

vGoodtimes said:
I'm assuming this clk140 constraint was removed. The UCF had it at 75MHz, which could be correct, but probably not.

If removing unrelated logic causes the design to work, I would be suspicious of timing constraints.
Click to expand...

thanks for the comment. I have three clocks in my design, I have not used any signal from a clock domain in another clock domain. between the clock domains I have put a FIFO to avoid CDC.
 

do those chipscope images use the data same as trigger, you did not show the expanded view of the DataPort and TriggerPort to see if you use the same signals.

I looked over your settings and there doesn't appear to be any use of the optimizations that actually do not work properly in all designs. My advice don't ever enable the logic optimization features they can corrupt a perfectly working design in some rare cases. Xilinx even admits this but never officially divulged the information in a software errata (at least any that I've run across). They also stated they were never going to fix it too (already focused on Vivado).


1. You never did state what your utilization was.
2. Nor have you shown what the unconstrained paths report has in it.

If you have unconstrained nets and you have high utilization you would likely see the behavior you are seeing...all your logic included and something fails to meet timing giving erroneous results, removing some logic and the design meets timing with good results. The timing met/failed would be in the unconstrained paths.
 

thanks for the comment. those chipscopes show the same data. the data and trigger are the same. in the below Image I have shown the timing report.

there are two timing problem, but they are in the FIFO (which is xilinx's IP core). I don't know how I can fix them. are they important?
in the below image I shown the source utilization.

and these utilization report:






I think that I don't have high utilization.
thanks for your helps.
 

From my experience ISE is really bad with low utilization, which is what you have. I also notice your design (what little there is of it) is spread across 75% of the part, which usually results in timing problems unless the design is pipelined properly as ISE's placer many times does a poor job of placing critical path near each other.

Try increasing the effort levels on the placer and add the extra effort, also enable register retiming, which might help if you have areas that are not well balanced for the amount of logic between registers.

I also don't have the time right now to check what the two items in the middle of the die are. I'm assuming they are required and that part of the issue is the pin placement is not optimal to interface with those two IP blocks.

You know if you enabled the report in map you could have saved yourself the effort in posting a bunch of screen captures of the utilization. Just a code block of the entire report would have been much easier to post.

It would be helpful to see a detailed timing report of one or more of the failing paths, to see what is causing the failure. From what you've discussed in this thread earlier your clock frequencies don't seem that high that you would have these kinds of issues with such low utilization (assuming the placer did a better job than my low opinion of it).

I did notice that the one view shows a bunch of unconstrained paths, do you know for a fact that they don't matter?
 

thanks for your attention, you have always helped me. I don't know how to thank you.
I tried those points but nothing changed.
the timing fails in the FIFO. the source and the destination of the failed path are in my FIFO which I can't modify it.
and I don't know what I should do with unconstrained paths. and I also don't know why they don't matter. I googled it but I did not find any useful information about it.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…