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How to reduce interrupt latency of MSP430F1121

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niks

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Can anyone tell me how to reduce interrupt latency of MSP430F1121.
Im using port interrupt and TIMERA0 (CCIFG i.e. CCR0=timer value) interrupt.
this is very urgen for me
thanks in advance
niks
 

Hi

How do you serve de interrupt request!? C or assembly!?

I think if you use assembly the latency time will be short.

Best regards
Pendragon
 

Yes its true. But i converted same code to assembly . But interrupt routine there are same number of instruction im using in C .
 

What is delay between port change and your first instr of INT body ?
 

im working at ACLK=MCLK=SMCLK=7.3728MHz.
Time delay betn Intr and first instruction of Intr body is around 13uS.
I think this delay is too much almost 100clks. 130uS is instruction cycle time.
Can someone tell me solution/clarification for same
 

Are you triggering the INT on the right edge ? It cannot take 100 clks to get from port pin change to start of INT routine - it looks like your INT is configured for rising edge while you are looking at Falling edge (or Vice versa!)

Smokey
 

"The interrupt latency is 6 cycles, starting with the acceptance of an interrupt request, and lasting until the start of execution of the first instruction of the interrupt-service routine..." (slau049c.pdf)

So you have something wrong.

Check also "low power" mode settings.
 

i checked data sheet already.this is 6 clock cycles or those 6 steps mentioned. its not clear. and im not setting any low power mode.
 

Check if timer interrupt is not very often or very long and what happens when 2 or more (port and/or tmr) intrerrupts occur.
 

HI
Im able to solve the problem. Actually problem is after PUC its setting OFIFG i.e. Osc Fault Intr Flag. previously i didnt checked it cuz normally we take care of that bit only in MSP430F149/135. But F1121 we need not take care. Now im just resetting flag .
i got expected result.
anyway thanks for the help and interest u showed in solving problem
regards
~niks~
 

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