how to reduce high fanout

[eda_wiz]

attribute syn_maxfan

hi all,
my linter says high fanout (16) on some nets. Can anyone tell me how to reduce this ..

tnx

 

[linuxluo]

Hi,
You can use your sythesis tool to set constraints just like set_max_fanout 8, that means in your design the fanout is lower than 8.

 

[spacekim]

if you modify hdl source, refer to the document!

 

[pcking1972]

how to set internal clk ?

 

[pcking1972]

how to set internal clk ?

 

[cnz]

there is a paper that discusses the high fanout nets!
Hope to help you!

 

[synq]

fanout

you can limit the fanout from any net or output port or any register output by fairly using attributes in your vhdl or verilog file. Take for example in synplicity:

It would be

attribute syn_maxfan of [name of net or port]: signal is [fanout number say 10];

word of caution here:::

lesser fanout attribute on crictical timing nets set for more global clock resources consumption.

 

[Guest]

Actually the high fanout problem can be solved by physical implementation. Espically for the clock and reset signals!

 

[ttspice]

Lint tool just wants to remind you some signal having larger fanout,
it doesn't mean a real problem, you should review your design to see if it will cause a problem physically.

btw, you can change Lint rule to avoid such warning.

 

[Ohh2]

You can simply use logic or register duplication in your design.

 

[vsop]

In my past experience, this kind of warning from so called HDL assistant tool means nothing, so I never take them into considerations. And I also suggest not try to fix this kind of warning in the synthesis step, it will result in a larger design. Modern layout tools are able to deal with them very well.

 

[Al Farouk]

As a compromise between all suggestions to solve the problem, you can try the solutions of using attributes or buffer insertion then simulat your design and check the violation that my appear and enhance your design according to the results you get.
regards