1. It wont wait, it will just use the current version of "signal". so as signal updates, signal_4 will update.
You need to understand how HDL simulation works. Signal assignments cannot really occur instantaneously, so simulation has a concept of deltas, which are an infinitely small amount of time. Signals are scheduled to update a minimum of 1 delta (you can specify an actual time with an after statement - but remember this is just for simulation) when a signal on the RHS of the assignement (or a signal in a process sensitivity list) changes.
But remember this is just simulation. On real hardware all of these signal assignments will equate to wires and gates. So in theory there is no delay between assignments, which is simulated using the delta system.
2. concurrently (see above)
3. yes
4. You can use arithmetic functions like +, -, * if you use the correct packages. But you need to understand what logic will be produced.
5. I guess thats your assignment. Think about how you would do it with digital logic, not with VHDL. VHDL is a description language after all, not a programming language. If you dont know what the circuit should be, you cannot expect to describe it with VHDL.