How to read and write image on FPGA using VHDL

[mehul03ec]

I like to read image from harddisk and process on FPGA and again processed image to be stored on Harddisk. So anyone can provide module/code to read and write for (vhdl code). I am using DE2 board.

 

[Iamventure]

Hi, Since the DE2 board has RS232 and Ethernet, you can use either of these to interface with the PC.
Using RS232, from PC you can send / receive data with the help of hyperterm.
For using Ethernet, i think you have to use Embedded OS if your board supports this.
Now if you are looking for the FPGA to load the images from Hard disk directly, then you are introducing the OS concepts into the FPGA. I say this because to read a file, the FPGA should understand the filesystem and filesystem is a feature of the OS.
So either you can proceed here to port Embedded OS to FPGA or if you want to process the images and can take care of sending it to FPGA,
use a C program in your PC to convert the image to streaming data and send it through RS232.

 

[mehul03ec]

Thanks for reply,
Now can you tell me how can i transfer image from PC to FPGA using RS232. Do i have to use any driver for that or i have to write the code?
Please elaborate.

Hi, Since the DE2 board has RS232 and Ethernet, you can use either of these to interface with the PC.
Using RS232, from PC you can send / receive data with the help of hyperterm.
For using Ethernet, i think you have to use Embedded OS if your board supports this.
Now if you are looking for the FPGA to load the images from Hard disk directly, then you are introducing the OS concepts into the FPGA. I say this because to read a file, the FPGA should understand the filesystem and filesystem is a feature of the OS.
So either you can proceed here to port Embedded OS to FPGA or if you want to process the images and can take care of sending it to FPGA,
use a C program in your PC to convert the image to streaming data and send it through RS232.

 

[tariq786]

Please look at opencores.org. They have Rs232 as well as ethernet mac core.