[SOLVED] How to re-synthesize a circuit with ABC synthesizer?

[amin-ea]

I am trying to re-synthesize the benchmark circuit such that they only consist of 4-input gates, specifically ISCAS85 benchmarks available at <http://www.pld.ttu.ee/~maksim/benchmarks/iscas85/bench/>.

For instance, c432 circuit. Since, c432 circuit has several gates with over 4-inputs (up to 9 inputs), I want to reconstruct it with gates of maximum 4 inputs.

I am using ABC Berkeley's synthesis tool to do this. I have used the following commands:
```
abc 01> read c432.bench
abc 02> write_bench c432new.bench
```
The above commands have some problems:

1) c432new.bench is constructed with LUTs instead of gates (NAND, OR, ...)

2) how to restrict the number of fan-ins (# of gates inputs) to 4?

3) since ABC is based on AIGs(And Invert Graph), it synthesizes the network with AND and NOT gates only. But how to synthesis based on different types of gates?

How C432 is constructed in the first place? Is there any other elegant synthesizer to that?

Consider the Netlist files or verilog files of all circuits are available.

Could you please help me with this?

Best Regards.

 

[ThisIsNotSam]

I am trying to re-synthesize the benchmark circuit such that they only consist of 4-input gates, specifically ISCAS85 benchmarks available at <http://www.pld.ttu.ee/~maksim/benchmarks/iscas85/bench/>.

For instance, c432 circuit. Since, c432 circuit has several gates with over 4-inputs (up to 9 inputs), I want to reconstruct it with gates of maximum 4 inputs.

I am using ABC Berkeley's synthesis tool to do this. I have used the following commands:
```
abc 01> read c432.bench
abc 02> write_bench c432new.bench
```
The above commands have some problems:

1) c432new.bench is constructed with LUTs instead of gates (NAND, OR, ...)

2) how to restrict the number of fan-ins (# of gates inputs) to 4?

3) since ABC is based on AIGs(And Invert Graph), it synthesizes the network with AND and NOT gates only. But how to synthesis based on different types of gates?

How C432 is constructed in the first place? Is there any other elegant synthesizer to that?

Consider the Netlist files or verilog files of all circuits are available.

Could you please help me with this?

Best Regards.

Tere!

1) the circuit is not contructed with LUTs, it is a specific format that synthesis researchers keep alive for reasons that are beyond me
2) during the mapping stage. if your library only has 4 input gates, the circuit will be mapped to 4-input elements
3) AIG is the underlying structure. it doesn't mean the final synthesis output will be only ands and invs. mapping still takes place.

why wouldn't you consider using verilog descriptions of the iscas benchmarks and run a commercial tool like genus/dc?

 

[amin-ea]

Tere!

1) the circuit is not contructed with LUTs, it is a specific format that synthesis researchers keep alive for reasons that are beyond me
2) during the mapping stage. if your library only has 4 input gates, the circuit will be mapped to 4-input elements
3) AIG is the underlying structure. it doesn't mean the final synthesis output will be only ands and invs. mapping still takes place.

why wouldn't you consider using verilog descriptions of the iscas benchmarks and run a commercial tool like genus/dc?

Thank you for clarification sir.

All i want is .bench formats circuits with gates of maximum of 4-inputs.

I am new to ABC. Would you please show me the steps to perform this? or provide a link if there is 4-input version of benchmark circuits?

about (1). I said that because the generated output file was like
" new_G9_ = LUT 0x7 ( new_G16_, new_G15_ )" how to change "LUT 0x7" to a gate name.

about (3). I have tested ABC "write_bench" command for ITC99 ciruit (b01_c) the output file (b01_cnew.bench) was only contains BUF , NOT , AND gates while the original one has different types of gates.

Thank you for your time.

 

[amin-ea]

Thank you for clarification sir.

All i want is .bench formats circuits with gates of maximum of 4-inputs.

I am new to ABC. Would you please show me the steps to perform this? or provide a link if there is 4-input version of benchmark circuits?

about (1). I said that because the generated output file was like
" new_G9_ = LUT 0x7 ( new_G16_, new_G15_ )" how to change "LUT 0x7" to a gate name.

about (3). I have tested ABC "write_bench" command for ITC99 ciruit (b01_c) the output file (b01_cnew.bench) was only contains BUF , NOT , AND gates while the original one has different types of gates.

Thank you for your time.

I've realized that if we strash (structural hashing) the input file we can write it with gate instead of LUTs by the following code:

abc 01> read c432.bench

abc 02> strash

abc 03> write c432new.bench

however the output file still is consists of (2-input) AND and NOT gates !

is there any specific library or code to include or change to have different types of gates with arbitrary fanins?
Could you please share your experience? Any help will be greatly appreciated.

 

[ThisIsNotSam]

I've realized that if we strash (structural hashing) the input file we can write it with gate instead of LUTs by the following code:

abc 01> read c432.bench

abc 02> strash

abc 03> write c432new.bench

however the output file still is consists of (2-input) AND and NOT gates !

is there any specific library or code to include or change to have different types of gates with arbitrary fanins?
Could you please share your experience? Any help will be greatly appreciated.

last time I have touched ABC I was still in undergrad, ~2 decades ago. I can't help much. look for how to use a library with ABC, there should be a way.

 

[amin-ea]

Finally. I've got the solution. All i need was a customized library (a liberty file) with only 4-input gates.

The library:
https://drive.google.com/file/d/1mGYhNdBm_t-0TbDFUnSvZl9jPLyKAsEo/view?usp=sharing

Then using the following commands we can get the desired .bench file:

abc 01> read c432.bench
abc 02> read_lib Mylib.lib
abc 03> map
abc 04> write_bench c432new.bench
abc 05> write c432new.blif

Since c432new.bench is represented with LUTs (due to ABC, AIG mapping restriction)
We also write the mapped circuit to .BLIF file to identify each LUT corresponds to what gate.

Thanks to Sam for mentioning the library .