How to put constraints on latch-based design?

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Dear all,
Is it possible to synthesize & verify a RTL latch-based design using DC? Or for latch-based designs, there're methodologies rather than DC?
I know there's a way to create two non-overlapping clocks using create_clock, but not sure if DC/PT can verify the timing after PR, that the skew between the two non-overlapping clocks are balanced.

For example, if ck1 and ck2 are constrained below in DC, will DC/PT report violations that ck1_PR overlapped ck2?
 

You can always use the latch based designs in Dc and Primetime, it is all supported. The biggest problem is that you will face during DFT and time borrowing. Both these problems cause the usage of latch based designs to be minimum in industry. Latch based designs are done in custom designs where you can run spice simulations to get the timing margins.
 
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