how to protect my RTL source code?

[liuzhili]

How to encrypt synthsisiable RTL code to only behaviorable code?
so that others only could use these code to simulate it but can not synthsis it!
so far as I know , vcs support it ,use option +protect, but how about other simulator? like ModelSim ,and so on. If do,how to?
Thank you very much!

 

[maestor]

This is what I would do...

Write your RTL.
Synthesize it.
Imaging is a X!linx device, build it with ISE
Create a post place and route simulation model...

there are some options there like simulator you use, VHDL or Verilog and that kind of thing...

it generates a totally device specific code with lots of hdl lines, it can be simulated bloody slow and it's encrypted (it's not giving awya your RTL), just a target specific version of it.


-maestor

 

[ljkong]

for modelsim,
you can use vcom -nodebug to do it.
good luck.

 

[eda_wiz]

try this tool ..Verilog Obfuscator
http://www.semdesigns.com/Products/Obfuscators/VerilogObfuscator.html

 

[gaonkc]

u can use cadence tools to pretect it

 

[seanwu]

It only protect seeing source code.

 

[maestor]

Hi gaonkc,

Could you talk a bit more about those C@dence tools?

Thx,

-maestor