How To Proceed If ERROR is Coming in Verification ??

[uditkumar1983]

Hi Friends,
I wants to know about if am doing verification(Functional) of my core using simulation, than whats general step I have to follow for finding and fixing bug within specified time limit .

Suppose you are running any test case since four days then you find that any error is coming then you will suspend or terminate the simulation, and you are having less time for delived of your project then so how you will proceed ..

Please Give me your suggestion ..waiting for your replies.....

Regards

 

[pintuinvlsi]

I think you have to fix this bug before delivery if there is some genuine problem in chip. Since functional failure may cause a respin of chip. So it is better to debug at highest priority and then deliver it.

Hope answers you question.

Regards,
pintuinvlsi

 

[uditkumar1983]

Hi Pintuinvlsi,

I am agree with you but I am asking general flow (Steps) of debugging bug ,So that you can find any type of error easily without wasting more time , I think now u can understand whats I wants to know ...

Thanks in Advance ..
Regards

 

[rsrinivas]

In front end verification u have the testcase which when fails shows the exaxt data that was fed to the core at that time and the particular branch of the code that gave u error.
so u can go and debug the code(RTL) or u may end up finding tat the fed in data was illegal....!!!!!!!!!
Note: if u get an error during verification it doesn't necessarily mean thats a bug in ur RTL it may be a bug in ur Verification code itself like not proper constraining ur design.

Regards
Srinivas