How to plot jitter tolerance in cadence with verilog-A behavior model

[LiaoJJ]

Hi,
I design a 1/5 rate clock and data recovery (CDR) , and I have designed a behavior model with verilog-A.
But I have no idea how to plot jitter tolerance to verify the specification.
The papers I research mentioned can use a checker to check the recovered data and PRBS data to get bit error rate(BER), but it is time-consuming.
Does everyone have relevant experiences?
Thanks a lot!

 

[dick_freebird]

Jitter comes from nonideal stuff. Has your veriloga any
coverage of things like

delay dependence on input slew rate
delay dependence on power supply voltage
application circuit's lead inductance
application circuit's incoming voltage ripple and filter cap ESL, ESR and C
transistor history effects, self-noise of various forms

This analysis would usually be done with transistor level
models and hopefuly with circuit level parasitics and noise
sources represented.