Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to optimize the buck efficiency between switching frequency and powerfet size?

Status
Not open for further replies.

sanlang

Newbie level 1
Newbie level 1
Joined
Oct 16, 2007
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,287
When we increase the switching frequency, result in increase of switch loss if we keep the same size powerfet.
By reducing the powerfet to reduce the switching loss, which will increase the Rds_on of powerfet ,result in the increase of conduction loss.

My question : Is there any formular to optimize effeciency between the switching freqency and powerfet ( or other factor I didn't mention here)

Thanks!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top