Hello,
I am synthesizing combinational circuits with Design Compiler from Synopsys, and I would like to optimize each circuit for the delay, power, and area independently i.e. three netlist in total (one for each optimization in each component) . I am using following constrains for area and delay, but I don't know how to optimize for power yet. Can you advise how to do it?
Power:
"ANY ADVISE"?
Delay:
set_max_delay 0 -from [all_inputs] -to [all_outputs]
Area:
set_max_area 0.0 -ignore_tns
thanks