How to multiply a pulse at the input of a circuit by 3?

[E-goe]

Hi guys

Anybody has an idea to multiply a pulse at the input of a circuit by 3.

I need an implementation with CMOS gates

Greetz E-goe

 

[truebs]

Re: Multiply pulse by 3

Well just to multiply any signal by 3 we can use an amplifier (called multiplier in this case ) with a gain =3 .
Opams are ideal choice.

 

[FoxyRick]

Re: Multiply pulse by 3

Hi E-goe,

Do you want:

1. 3 output pulses for every input pulse (pulse train)

2. A pulse 3 times longer than the input pulse (pulse stretch)

3. A frequency 3 times the input frequency (frequency multiply)

4. As truebs said, 3 times the amplitude of the input pulse

???

Cheers,
FoxyRick.

 

[E-goe]

Re: Multiply pulse by 3

Hi FoxyRick

I need the following:
A pulse 3 times longer than the input pulse (pulse stretch)

Thanks for the reply

Greetz E-goe

 

[IanP]

Re: Multiply pulse by 3

So what you basically need is a device that will measure the time of a pulse and generate a pulse of 3 x the input pulse.
For this task you will have to employ a microcontroller that will follow the above procedure ..

 

[FoxyRick]

Re: Multiply pulse by 3

Hmmm... you picked the hardest one.

I probably can't help much here, but I'll try to point in the right direction.

First, what is the minimum and maximum width of the input pulse? Does the ouput pulse have to start simultaneously with the input pulse, if not, what delay is acceptable (can the ouptut pulse start *after* the input pulse has stopped)?

Measuring, either by microcontroller or by any other digital counter means is possible if the pulse is long enough, and technically you could build it in CMOS. But it would be big...

Or you could measure it the old-fashioned analogue way, by charging a capacitor with a fixed current, then discharging the capacitor with a lower current and using this to start/stop the output.

Like this, I think, for an ouput that starts simultaneous(ish) with the input:

0. Make sure the capacitor is discharged to begin with
1. Input pulse rises...
2. Immediately start output pulse
3. While input is high, gate the constant current into the capacitor
4. Capacitor charges to a voltage proportional to the pulse width
5. Input pulse now falls...
6. Decouple capacitor from input
7. Discharge capacitor with a constant current (1/2 of the charging current)
8. Capacitor takes twice as long to discharge, giving a total 3x ouput
9. When capacitor reaches zero volts, stop output pulse
10. Reset logic to wait for next input pulse

I can sort of visualise this, but it's not my area of expertise (I'm not sure I have one, if I have it's simple digital logic and microcontrollers).

I'm not sure if you could build the comparator needed to detect zero volts with CMOS. I suppose you could arrange a non-zero end-point capacitor voltage at the trip level of the logic.

Hope this is some help, it's about the best I can do. Hopefully someone will come up with a nice, easy solution that makes mine look daft.

Cheers,
FoxyRick.