How to model smart primitives in verilog?

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How do I model smart primitives in Verilog?
Example: I should design a majority function that can take any number of inputs(finite).
I tried with FSM. The problem was: I could not call it and use it as regular primitives like AND, OR etc.

My Code: (I cannot use this code as I do with standard primitives.)

module s_majority(in,out,clk,rst);
// In - one bit input, clk - clock, rst - reset
  input in,clk,rst;
// out - output
  output reg out;
// Declaring local parameter for the state machine
  localparam s0=0;
// Declaring state machine case variable
  reg machine;
// count_zero - counts zeros. count_one - counts ones.
  reg [31:0] count_zero,count_one;
  always@(posedge clk) begin
    if(rst) machine <= s0;
    else machine <= machine;
  end
  always@(machine) begin
    case(machine)
      s0: begin
// Counting ones and zeros     
        if(in==1) count_one=count_one+1;
        else if(in==0) count_zero=count_zero+1;
        else begin
            count_one=count_one;
            count_zero=count_zero;
        end
// Comparing counts of zeros and ones     
        if(count_one>=count_zero) out=1;
        else out=0;
     
      end
   
      default: begin
        count_one=0;
        count_zero=0;
        out = 0;
        machine = s0;
      end
    endcase
  end
endmodule

module tb();
  reg in,clk,rst;
  reg maj;
  integer i;
  wire out;
  s_majority i1(in,out,clk,rst);
  always #5 clk=~clk;

// Task to send inputs bitwise.
  task check;
    input [9:0] inp;
    begin
    #4 rst=1;
      for(i=0;i<10;i=i+1) begin
      #10 rst=0;
      in=inp;
    end
    end
  endtask

  initial begin
      clk=0;
    $dumpfile("tb.vcd");
    $dumpvars;
    $monitor("majority=%b",maj);
// Task call  
    check(10'b0000011101);
    maj=out;
    #10;
    $finish;
  end
endmodule