How to model mismatch between M3/M4 pair from this figure

[dkumar]

Hi,
In the figure below, I want to model the mismatch in M3/M4 device. (like may be say Vt mismatch)

I know how to do that for M1/M2, M3/M5 and M7/M8 pairs but how shell i do for M3/M4 pair.

thanks

 

[keith1200rs]

Mismatch analysis

You could either use the Monte Carlo models if you have them or simply add a small voltage source in series with the source of one of the transistors if you just want to see the effect of a Vt error.

Keith.

 

[dkumar]

Re: Mismatch analysis

yeah, i did that. like added a small voltage source at the gate of load transistors.
I was wondering, should i be doing small signal analysis (hand calculation) or large signal.
What i mean is, after putting a voltage source at the gate, should i consider the vdd to be zero and do analysis ? In that case, i would also consider the input transistor being off (as i should ground the inputs)


thanks

 

[keith1200rs]

Mismatch analysis

The voltage source should be in series with the gate or source. Vdd should be whatever it is designed to be for the analysis.

I think I am not understanding the question, I'm afraid.

Keith.

 

[dkumar]

Re: Mismatch analysis

hi,
I think what i am trying to say is, if i add the small voltage , say in series with the source of M3, that will come in between vdd and source right.

so,now the equation for current in M3 would become = kw/2l (vdd-vn-vth)^2

then i have following doubts:

1. is this value of current same as the current in M1 ( which ideally should be) and would be I/2?
2. This would mean i am doing large signal analysis without making small signal assumption for vn and not taking in to account the gm of transistors.
3.Or should i do that analysis in small signal sense , by considering the current in M3 as gm3*vn and then taking M3 as resistor of 1/gm3 and at the same time considering no current in M1/M2 (as no small signal input).

thanks

 

[keith1200rs]

Mismatch analysis

1. yes - that current is the same as M1 current, but now it won't be the same s I/2 because there is now an offset

You need large signal analysis assuming you are trying to find the effect on the output offset, not the effect on the open loop gain.

Keith.

 

[dkumar]

Re: Mismatch analysis

Hi Keith,
Thanks for the clarification. That was helpful.

At the same time, if i want to simulate the same circuit for systematic offset (not random offset), how should i go about doing it. This is a comparator and not opamp, so i believe i need to have some trick.

What i was thinking was, I put the input signals at Vcm and then see the output and then vary the voltage at one of the input terminal and see for what voltage value the comparator trips. But, this idea doesn't seem quite intuitive.

I was also thinking of doing the same by first putting the input nodes to ground and then varying the input.

could you please put some light on this.

thanks much.
-divya

 

[keith1200rs]

Mismatch analysis

For systematic offset I would put the maximum Vth difference on to the transistors then fix one comparator input somewhere in it's common mode range and DC sweep the other. If you are applying multiple offsets then you need to make sure you get the sign correct otherwise they may cancel whereas in reality they could add.

Keith.

 

[dkumar]

Re: Mismatch analysis

Hi,

Systematic offset measurement:
1. I didn't get you when you say 'put maximum vth difference on to the transistors'
2. Also, what do you mean when you say 'applying multiple offsets'. I believe i am not applying any offset from outside.

(just to make it better: there are bunch of inverters after the output of the comparator.)

Random offset measurement:
1. I guess we agreed on the fact that with the offset voltage at the source of M3, the quiescent current in M1/M3 will not be I/2. but, i believe for offset analysis we must have the inputs of M1/M2 at Vcm and that would mean, the current in M1/M2 would be same and which should be I/2. But, now that the source voltage of M3 is no same as that of M4, the current in them will be different. Rather one of them will have I/2 and other will have I/2 [tex:2aa5e9b6ad]/pm[/tex:2aa5e9b6ad] [tex:2aa5e9b6ad]/Delta[/tex:2aa5e9b6ad]. and this extra current in (say M3) would circulate locally (ie. M3 -> vn -> M3 ) and generate extra voltage at the gate of M3 which will get mirrored and appear at the output.

2. It above situation doesn't happen and the current in M1/M2 also changes form I/2 then how is it happening when the Vgs of both M1/M2 are same.

Hope i am making some sense?

thanks

 

[keith1200rs]

Mismatch analysis

I was assuming you were planning to find the maximum offset due to mismatches in all the transistors. So, one transistor out of each pair would need a voltage source adding. If you have Monte Carlo models it would be simpler just to simulate with those rather than go adding additional voltage sources everywhere. Also, you are only adding one mismatch parameter - Vth. Other transistor characteristics will have a mismatch which will affect performance as well.

Keith.

Added after 1 minutes:

By the way, I have mixed up the systematic and random offset. My earlier comment was really intended for random offset analysis.:

"For systematic [should read random] offset I would put the maximum Vth difference on to the transistors then fix one comparator input somewhere in it's common mode range and DC sweep the other. If you are applying multiple offsets then you need to make sure you get the sign correct otherwise they may cancel whereas in reality they could add."

Keith.

 

[dkumar]

Re: Mismatch analysis

Hi Keith,

Yeah, i want to find the offset due to mismatch in each pair of transistor and i was pretty much able to do that for all the other pair but for M3/M4. ( I also took M3/M5 as a pair)

But, i would again request you to please clarify on my question about the current in M3 and M4 branches when there is a offset voltage applied at the source of M3.

(which was: Random offset measurement:
1. I guess we agreed on the fact that with the offset voltage at the source of M3, the quiescent current in M1/M3 will not be I/2. but, i believe for offset analysis we must have the inputs of M1/M2 at Vcm and that would mean, the current in M1/M2 would be same and which should be I/2. But, now that the source voltage of M3 is no same as that of M4, the current in them will be different. Rather one of them will have I/2 and other will have I/2 3$/pm 3$/Delta. and this extra current in (say M3) would circulate locally (ie. M3 -> vn -> M3 ) and generate extra voltage at the gate of M3 which will get mirrored and appear at the output.

2. It above situation doesn't happen and the current in M1/M2 also changes form I/2 then how is it happening when the Vgs of both M1/M2 are same.

)



Also, how would you suggest me to go about measuring the systematic offset? As i believe, the path from positive input to output is different from that of negative to output.

thanks

-Divya

 

[keith1200rs]

Mismatch analysis

M7 and M8 are also a pair for matching purposes.

I don't understand what you are really trying to say in the rest of your post. Input offset is the voltage you need to apply to the input to get zero offset on the output. In the case of a comparator, zero offset on the output could be considered to be mid rail.

If you are ignoring M1/M2 offset and just looking at M3/M4 then the input offset will be the voltage difference that has to be applied to M1/M2 gates to make the output mid rail (less any systematic offset, if you are simply looking at the random part). That will require a current difference in M1/M2 drains to compensate for the different Vt of M3/M4.

I think we are probably saying the same thing, but we are looking at it from different directions.

The easiest way to analyse this is probably to simulate it.

Keith.

 

[dkumar]

Re: Mismatch analysis

HI Keith,

I was once again looking at analyzing the offset and i have this small doubt.

For the offset considerations, i considered M1/M2 pair and M3/M4 pair. Now, I am not sure that shell i take M3/M5 and M4/M6 pair or M5/M6 pair or all the of them?


I guess i should take all of them but just wanted to gets some confirmations.

thanks

 

[keith1200rs]

Mismatch analysis

Unfortunately you have to analyse almost everything. A mismatch between M4/M6 will have an effect (although M4 and M6 may not be the same size), but so will a mismatch between M5/M6.

Keith