[SOLVED] How to model jumper links or any crosspoint device?

Hello all,

I want to be able to *model* a collection of jumper links in VHDL.

I have some bidirectional signals that will be contained within the jumper links.

I essentially just want to emulate a wire, something like the following.
PIN4_LHS <= PIN4_RHS;
PIN4_RHS <= PIN4_LHS;

In total the data path would look something like this
fpga_LHS -> databus1_LHS -> PIN4_LHS -> PIN4_RHS -> databus1_RHS -> fpga_RHS
fpga_LHS <- databus1_LHS <- PIN4_LHS <- PIN4_RHS <- databus1_RHS <- fpga_RHS
Where the above can be broken down into sections that follow
board_LHS | test_board & Jumper_links | board_RHS

The board_LHS or RHS have buffer models that are controlled by directional and enable pins of the fpga. The outcome is that databus1 is ether assigned or set as 'Z'

Ideally the model can be updated by rewiring the jumper link pin allocation, rather than signals assigned during board_LHS or RHS component instantiation


Many Thanks,
Wes

Signal connections in usual FPGA technologies are unidirectional, there's no thing like a bidirectional buffer.

Internal bidirectional busses with tristate buffers can be modelled to a certain extend but are actually translated to unidirectional connections and muxes. There can be only one driver to the bus at a time and the logic can be only synthesized if the driver can be determined.

wesleytaylor said:

Hello all,

I want to be able to *model* a collection of jumper links in VHDL.

I have some bidirectional signals that will be contained within the jumper links.

I essentially just want to emulate a wire, something like the following.
PIN4_LHS <= PIN4_RHS;
PIN4_RHS <= PIN4_LHS;

Click to expand...

The following link might get you going. It is a model for a bi-directional switch and a resistor.
**broken link removed**

Kevin Jennings

I presume that fpga_xxx in the original post indicates synthesizable VHDL. The linked bi-directional switch will be hardly synthesizable.

FvM said:

I presume that fpga_xxx in the original post indicates synthesizable VHDL. The linked bi-directional switch will be hardly synthesizable.

Click to expand...

The original post said "I want to be able to *model* a collection of..." (coloring mine)

Kevin

To clarify the problem at hand.

1. I have a synthesisable bit of code on the fpga.
2. The board that the fpga sits on is modelled with some non-sythesiable models which represent 16245 buffers.
3. These buffers have direction & enable pins that are managed via the fpga.
4. The data signals that go into these 16245 buffers leave the fpga board and go onto a test card.
5. On the test card they are then routed through a matrix of jumper pins.
6. From there they travel to another card with 16245 buffers & an fpga.

Where point 5. can be viewed as a wire delay. I'm currently using K-J's link.

Thank you