How to model asynchronous clock in DC compiler?

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shiv_emf

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How to model asynchronous clock in DC compiler???

if suppose v hav two clocks in design .. both r originating from different sources .. wht cud be probable solution??
Shiv
 

Re: asynchronous clocks

If they are async clocks, i don't think you want to model them in DC. For timing/synthesis purpose, just define them as false paths. Then make sure that the signals that pass between the async clock domains are synch'ed properly.

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