May 19, 2011 #1 A a_shirwaikar Newbie level 6 Joined Mar 1, 2011 Messages 11 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,376 hey, does anyone have any good links or ideas on how to minimize clock power specifically in ASIC based designs?
hey, does anyone have any good links or ideas on how to minimize clock power specifically in ASIC based designs?
May 19, 2011 #2 ckshivaram Advanced Member level 6 Joined Apr 21, 2008 Messages 5,060 Helped 2,150 Reputation 4,306 Reaction score 2,088 Trophy points 1,403 Location villingen (Germany) / Bangalore Activity points 30,088 Re: minimize clock power see this http://csg.csail.mit.edu/6.375/6_375_2007_www/handouts/lectures/L12-Clock-and-Power.ppt ARM Information Center http://www.cse.psu.edu/~mji/asic/tutorial-clock.pdf **broken link removed**
Re: minimize clock power see this http://csg.csail.mit.edu/6.375/6_375_2007_www/handouts/lectures/L12-Clock-and-Power.ppt ARM Information Center http://www.cse.psu.edu/~mji/asic/tutorial-clock.pdf **broken link removed**