How to minimize area in DC synthesis ?

[mikel262]

area minimization

How to minimize area in DC synthesis. Any switches beside set_max_area 0?

 

[edacrack]

Re: area minimization

the tool always try to minimize the area if the timing constraint is satified

 

[horzonbluz]

Re: area minimization

Hi, beside set_max_area 0.0, you can set some variable to optimise your
design and reduce the areaof your design.
set_flatten false;
set_structure true -timing true;
transform_csa -duplicated;# If you use many arithemetic in your design
You can set dont use some cell to increasing speed and reducing area of your designware components too.
If the timing constraint of your design is satified, you can run area optimize using DC tool.