[SOLVED] How to meet two libraries simultaneously during synthesis ?

HI All.

I'd like to synthesize a design which meet two timing libraries simultaneously.
To be more specific, I have two libraries whose voltage are 3.3V and 1.8V
The design must support the two conditions when operating at 3.3V and 1.8V respectively.

However, I don't know how to synthesize a design which meet two timing libraries simultaneously instead of two runs.
I have searched for the related topic but found no result.
The following article is similar but it seems no appropriate for me
https://www.edaboard.com/threads/189555/

Could you give me some hints or key words about this issue ?
Thanks greatly.

PoLo

When you said two libraries, I guess that is the same std cell but with two voltage characterization?
If yes, during the synthesis and PnR, you should used the MMMC, to indicate you have two pvt for the setup.

rca said:

When you said two libraries, I guess that is the same std cell but with two voltage characterization?

Click to expand...

yes, the same std cell operating at different PVT but not merely min/max libraries
what I means is two voltage levels such as 3.3V for slow and 1.8V for fast mode

rca said:

If yes, during the synthesis and PnR, you should used the MMMC, to indicate you have two pvt for the setup.

Click to expand...

It seems that MMMC is good way for this problem. However, MMMC is often used in PnR.
But I have hardly known that MMMC is applied in synthesis.
Does Synopsys Design Compiler support MMMC ?
Chapter 10: Using Design Compiler Topographical Technology Optimizing Multicorner-Multimode Designs in Design Compiler Graphical ? <== this chapter ?


P.S.
By the way, I'd like to know more clearly about MMMC(Multi-mode Multi-corner)
what's the difference between mode and corner ?

1. the different constraints over the same design/libraries = different modes ?
2. the different libraries over the same design/constraints = different corner ?
3. a design contains voltage islands but always operating under the same condition = not mode/corner ?
4. logical variation = different mode ? physical variation = different corner ?
5. a design with test mode under different PVT libraries = different mode and different corner simultaneously ?


Anyway, Thanks for your helps.
PoLo.

MMMC :
Multi Mode : Differen modes. This can be functional,Test modes or any other modes. Inside functional mode, it can have many many modes like, PLL works at half frequency or works at high frequency.
Multi corner : different corners. Corners will be varied depends on technology node.

your understandings are correct as you mentioned.

As of now, DC is not matured enough to consider MMMC even though synopsys claim .
Then how to proceed?.
1. coming back to your first question . Design need to work at 3.3V and 1.8V.
When design is switching between two voltage levels, the operating frequency will vary. Pick the highest operating frequency(it should be with 3.3V) and synthesize the design. In the next iteration , check the timing with 1.8V and see if any paths are violating. If its more than 50%, the library characterization might be an issue. If its less than 20% of the design is violating, Write the critical paths and try to optimize these paths only( Group the paths and apply critical range).

If the design is very sensitive and unable to track the results between Pre-PNR and Post-PNR results only follow above techniques else safely you can follow single operating conditional synthesis.

Let me know if you see any issues.

First thanks for your kindly help, sam

sam536 said:

MMMC :
Multi Mode : Differen modes. This can be functional,Test modes or any other modes. Inside functional mode, it can have many many modes like, PLL works at half frequency or works at high frequency.
Multi corner : different corners. Corners will be varied depends on technology node.

your understandings are correct as you mentioned.

Click to expand...

As of now, DC is not matured enough to consider MMMC even though synopsys claim .

Click to expand...

Currently, I use Design Compiler MMMC flow to synthesis the design and optimize the MMMC concurrently.
It seems that it costs longer time to synthesize compared to previous single condition.

However, it's not obvious that there is potential issue when using Design Compiler MMMC flow.
Could you share me about your experience?

Then how to proceed?.
1. coming back to your first question . Design need to work at 3.3V and 1.8V.
When design is switching between two voltage levels, the operating frequency will vary. Pick the highest operating frequency(it should be with 3.3V) and synthesize the design. In the next iteration , check the timing with 1.8V and see if any paths are violating. If its more than 50%, the library characterization might be an issue. If its less than 20% of the design is violating, Write the critical paths and try to optimize these paths only( Group the paths and apply critical range).

If the design is very sensitive and unable to track the results between Pre-PNR and Post-PNR results only follow above techniques else safely you can follow single operating conditional synthesis.

Click to expand...

In the above, could I summarize that the point is "incremental compile" and "ECO" ?
The most troublesome issue is that when I fixed one violated path, another safely path emerge as violated path.
This is why I seek for MMMC solution.

Let me know if you see any issues.

Click to expand...

Thanks for your kindly help again.

Best Regards.
PoLo