How to measure the DFT netlist's quality?

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u24c02

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Dear all.
I'm trying to score about DFT netlist output.
But How to measure the DFT netlist's quality?


I'm not sure from where to start. Does anyone have any Ideas?
 

I mean DFT inserted synthesis netlist.

How can I beleve the result of synthesis netlist from someone?
 

u24c02 said:
How can I beleve the result of synthesis netlist from someone?
Click to expand...
If the person who designed the code was incompetent and if the person doing the scan insertion is incompetent at doing their jobs then you can just assume the result you get is garbage and just ask for the original synthesis output and insert scan yourself...assuming that the person receiving the netlist is not incompetent too.

Unless you do it yourself you have to assume anything you get was done correctly or request the reports from scan insertion. As I've been out of the ASIC arena for decades there may be more tools than just scan insertion for DFT. Most of what I learned about DFT was primarily on the design side, i.e. designing the RTL so that scan insertion would ensure near 100% coverage as there wasn't any coding issues that would prevent detecting a fault.
 

Thanks Sir, if I took the incomplete netlist (not dft) from someone, then how can I check without assume? Is there any objective way to check? And also when included dft , not assume.
 

Hello,

When you get the scan inserted netlist, you just read back netlist in some EDA tool, and you can generate the report whatever you want to check. During DFT insertion also you can check the generated report.
 

Sorry? What do you want to said What kind of some EDA tool? Also what kind of check list in there? I mean what should I check in report? Also DFT.

Do EDA tool tell me like this? Sir your netlist are not good. Please check again~..
 

Yea. I know netlist is not good. What do you mean by not good? Does it mean that there are some missing information/any other issues.
Can you please list down that which things are there in netlist than you can say that netlist is not good.
So it just like first prepare list what you want to check.
Please clarify what do you mean by netlist is not good.
Is functional specs are not meeting or any other issue?
 

That expression netlist not good is meaning like this there are some mismatch between rtl and netlist.
More especially, what if I had insert clock gating but I can't find clock gating in netlist. Or I inserted power gating cell to netlist but I can not find power gating cell..etc.. does it make sense?
 

You can do formal verification between RTL and Synthesized Netlist using Formality tool or other logic equivalence checking EDA tool. So by this, you can have a mismatch at clock input logic cone due to clock gating cells.
You can also control optimization during Synthesis as it might be optimized due to some reason.
 

Hello u24c02,

As ads-ee has explained, I would also like to say that it is like a chain-of-trust which remains unbroken.
It is a rare case that you will get an untrusted netlist for Dft insertion. You see this is why softIPs are so popular. A fabless company in most cases will buy softIPs and then the internal design team will proceed to synthesis, dft, etc.

"How can I believe the result of synthesis netlist from someone?"
Well you ought to have some reference point. The reports of the first scan-inserted netlist becomes your 1st reference. Now suppose there is a change in the RTL and a scan-inserted netlist is again generated along with the reports. You can now compare the new reports with the old reports.
 

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