****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : hardenSbox_1
Version: D-2010.03-SP1
Date : Sun Aug 23 10:18:39 2015
****************************************
Operating Conditions: typical Library: NangateOpenCellLibrary
Wire Load Model Mode: top
Startpoint: ins_lookup/outPut_reg_7_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: out_port[7]
(output port)
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
hardenSbox_1 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
ins_lookup/outPut_reg_7_/CK (DFF_X2) 0.00 0.00 r
ins_lookup/outPut_reg_7_/Q (DFF_X2) 0.16 0.16 f
ins_lookup/outPut[7] (lookUp) 0.00 0.16 f
out_port[7] (out) 0.00 0.16 f
data arrival time 0.16
--------------------------------------------------------------------------
(Path is unconstrained)
As i have bolded above, the critical path delay is reported 0.16, the problem is whatever i change combinational part of my design, this number won't change. i have noticed that DC start point is a register and endpoint is a port , and this path is identical in my different designs then i changed startpoint to a input port, and i try "report_timing -delay max -through ins_lookup/indexX[3]" and the results are as follows:
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : hardenSbox_1
Version: D-2010.03-SP1
Date : Sun Aug 23 10:24:45 2015
****************************************
Operating Conditions: typical Library: NangateOpenCellLibrary
Wire Load Model Mode: top
Startpoint: indexX[3] (input port)
Endpoint: ins_lookup/outPut_reg_7_
(rising edge-triggered flip-flop clocked by clk)
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
hardenSbox_1 5K_hvratio_1_1 NangateOpenCellLibrary
Point Incr Path
--------------------------------------------------------------------------
input external delay 0.00 0.00 r
indexX[3] (in) 0.00 0.00 r
ins_lookup/indexX[3] (lookUp)<- 0.00 0.00 r
ins_lookup/U1368/ZN (INV_X4) 0.03 0.03 f
ins_lookup/U1167/ZN (NAND2_X2) 0.09 0.12 r
ins_lookup/U778/ZN (INV_X4) 0.05 0.16 f
ins_lookup/U1204/ZN (AOI21_X2) 0.07 0.24 r
ins_lookup/U1271/ZN (INV_X4) 0.01 0.25 f
ins_lookup/U924/ZN (AOI22_X2) 0.08 0.33 r
ins_lookup/U1252/ZN (INV_X4) 0.01 0.34 f
ins_lookup/U1378/ZN (OAI33_X1) 0.11 0.45 r
ins_lookup/U1177/ZN (NOR2_X2) 0.03 0.48 f
ins_lookup/U922/ZN (OAI221_X2) 0.05 0.53 r
ins_lookup/U915/ZN (AOI22_X2) 0.03 0.56 f
ins_lookup/U902/ZN (OAI221_X2) 0.11 0.67 r
ins_lookup/U1238/ZN (INV_X4) 0.02 0.69 f
ins_lookup/add_1_root_add_2646_2_U1_1/CO (FA_X1) 0.13 0.82 f
ins_lookup/add_1_root_add_2646_2_U1_2/S (FA_X1) 0.18 1.00 r
ins_lookup/U809/Z (XOR2_X2) 0.12 1.12 r
ins_lookup/U1229/ZN (INV_X4) 0.02 1.13 f
ins_lookup/sub_1_root_sub_0_root_add_2654_U2_2/CO (FA_X1)
0.12 1.26 f
ins_lookup/sub_1_root_sub_0_root_add_2654_U2_3/CO (FA_X1)
0.12 1.38 f
ins_lookup/U966/ZN (NOR2_X2) 0.13 1.51 r
ins_lookup/U784/ZN (AND2_X2) 0.07 1.57 r
ins_lookup/add_0_root_sub_0_root_add_2654_U1_6/CO (FA_X1)
0.09 1.66 r
ins_lookup/add_0_root_sub_0_root_add_2654_U1_7/S (FA_X1)
0.14 1.80 f
ins_lookup/U721/ZN (AOI22_X2) 0.07 1.87 r
ins_lookup/U1225/ZN (INV_X4) 0.01 1.88 f
ins_lookup/outPut_reg_7_/D (DFF_X2) 0.00 1.88 f
data arrival time 1.88
--------------------------------------------------------------------------
(Path is unconstrained)