delay
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VHDL code portability
Hello all,
What is the best way to go about while doing VHDL coding for FPGA and not knowing the target device (atmel, actel, altera etc). Currently I try not to use vendor specific libraries, macros, primitives and instantiations as I know that these won't work if in the end I target the design on something I didn't think of in the beginning.
This also gives me problems as I need to write everything from scratch and optimization may not be best as the code is not device architecture specific.
I also run three synthesizers Leonardo Synplify Pro and XST to be sure none of them frowns on the code and it is acceptable by all giving me some confidence level.
What other techniques can be used in order to make sure that the code is acceptable by a large number of device vendors?
Thanks,
Delay (delayed by technology)
Hello all,
What is the best way to go about while doing VHDL coding for FPGA and not knowing the target device (atmel, actel, altera etc). Currently I try not to use vendor specific libraries, macros, primitives and instantiations as I know that these won't work if in the end I target the design on something I didn't think of in the beginning.
This also gives me problems as I need to write everything from scratch and optimization may not be best as the code is not device architecture specific.
I also run three synthesizers Leonardo Synplify Pro and XST to be sure none of them frowns on the code and it is acceptable by all giving me some confidence level.
What other techniques can be used in order to make sure that the code is acceptable by a large number of device vendors?
Thanks,
Delay (delayed by technology)