How to make the sub power domain and top power domain using same vss vdd

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themanh246

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Hi! I am a newbie in physical design. Recently, i downloaded i2c project from opencores to learning how to use fusion compiler. After i compiled PG std rail, i shown all my cell from a sub module is violated, it short VSS/VDD rail to cell's VSS/VDD. I did make an UPF file and create a power domain for those sub module and made its primary power and ground is VDD and VSS, but it still shown short.
I don't know where is the problem. Pls help me
Thank you very much

 

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not sure I understood the issue. You have 3 power domains that actually connect to the same VDD/VSS? If so, the short reported by the tool is a disconnect between what you are telling it and what you meant to do.
 

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It could be as simple as misordering pins (text input)
or miswiring (schematic). Start with tracing the two
supply nets to each of their connections, for that.

Inspect the layout for whether you believe a full
block is flipped VDD for VSS, or whether there is
a true, localized short made by some feature.

If bussing is orderly then shorts should be visually
obvious, "things crossing which should not" in the
highlighted net (which should be two), where the
"funk" is, is likely the short.

Physical design need your eyeballs trained to
"recognize the not-right" because what you get
from reports, is mostly just whining and not
advice.
 

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i did check it before, i sure that the cell flipped the right way, the VDD/VSS of those cell is connected to VDD/VSS rail
 

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ThisIsNotSam said:
not sure I understood the issue. You have 3 power domains that actually connect to the same VDD/VSS? If so, the short reported by the tool is a disconnect between what you are telling it and what you meant to do.
Click to expand...
i'm sorry for my bad at english, english is not my first language. I dont understand what you mean
 

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It looks like you created a scenario where you have 3 VDDs but they are all the same. You are confusing the tools by doing that. That is my guess.
 

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ThisIsNotSam said:
It looks like you created a scenario where you have 3 VDDs but they are all the same. You are confusing the tools by doing that. That is my guess.
Click to expand...
My scenario only have 1 VDD. I think the problem is about defining these pins. When i click at pin VDD/VSS of those violated cell, it not show the type or anything shown that it belong to VDD/VSS like the other

other net

I don't know how to fix it, the non-violated cell is auto defined belong VDD/VSS from the beginning
 

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When you say the cells don't have net membership that sounds like one of more "opens" if this is a post layout or predictive layout scene.

If it's front end then I guess your discontinuity is more metaphysical and I got nuthin'.

Seems to me the design kit for this adventure ought to have guidance about hooking up to foundry IP (whose IP is it, whose support are you entitled to?) that evidently is not yours and not understood?
 

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