How to make the main pole controlled by the load capacitor

[rambus_ddr]

I am designing a regulator. which uses a close-loop opamp and a bandgap to get double or high output voltage. But in my design, since output has accurate require, so the opamp open-lop gain must be enough high. So I use fold cascode (first stage) + PMOS+two resistors (second stage). But the main pole in the first stage output, so when i increase the load capacitor, the Phase margin decreases. How can i make the main move to second stage output. Please give me some advices, thanks.

 

[terryssw]

Re: How to make the main pole controlled by the load capacit

This main pole is controlled by your compensation cap, while your second pole is controlled by your load cap. This is the reason that the phase margin has decreased when you increase your load cap. If you want to the dominant pole be controlled by your load cap, you should use single stage opamp.

 

[rambus_ddr]

Re: How to make the main pole controlled by the load capacit

In regulator design, there must be two stages or three stages because the large output current. So the miller capacitor is seldom used because the reason you said. I have got some papers which use zero-pole to cancel the internal pole. Thanks your reply.

 

[hardings]

Re: How to make the main pole controlled by the load capacit

Can you give your function diagram?

 

[terryssw]

Re: How to make the main pole controlled by the load capacit

Are you using the source follower for your second stage?

By the ways, pole-zero cancelling has some potential problem, a doublet will be created if not exact cancellation are performed, than it would greatly affect the settling behavior of your regulator.

For large output current, do you consider to use class-AB output stage? This kind of stage can typically provide sink or source current which is about at least 20 times of your bias current.

 

[lunren]

Re: How to make the main pole controlled by the load capacit

Mabey you can try a LDO(linear regulator), opa(error amplifier) with one stage is enough, in such circuit, the main pole is determined by your load capacitor

 

[opamp741]

Re: How to make the main pole controlled by the load capacit

u need to make ur output pole dominant..for this u hav to make ur o/p stage gain stage (gain of stage2>gain of stage1)..
any comments guys??

 

[alphi]

Re: How to make the main pole controlled by the load capacit

I think Ti smps application note have many classic idea for loop control.

 

[flyinspace]

Can you provide your circuits or block diagram?
I have met a similar problem with you and I am confused with it too.

 

[santhoshv78]

Re: How to make the main pole controlled by the load capacit

You need to introduce a zero in the load capacitor. Generally for a load capacitor of 2.2uF, 6 to 10 ohm resistor in series will solve the problem in simulation. In realization this can be the ESR of the load capacitor.

 

[rambus_ddr]

Re: How to make the main pole controlled by the load capacit

Yes, in ti's LDO paper, they often use two capacitor,one with ESR is large capacitor, the other is a small capacitor without ESR. The first capacitor and resistor create a zero to cancel internal pole. And in their design, there is also a capacitor between the op output and the op input, why use the capaciotr and how to use this capacitor. who have any advice,please show there.