paulinesean
Newbie level 3
I'm designing a traditional VCDL DLL which
is consist of PD, charge pump and voltage control delay line
, and I take different delay edges from VCDL to form
different delay clocks. However, the DLL can lock to 1 or 2 cycles
or more. The generated different delay clocks are not
what I expect if DLL lock to 2 or more cycles. Is there any way can make DLL only lock
to 1 cycle?
is consist of PD, charge pump and voltage control delay line
, and I take different delay edges from VCDL to form
different delay clocks. However, the DLL can lock to 1 or 2 cycles
or more. The generated different delay clocks are not
what I expect if DLL lock to 2 or more cycles. Is there any way can make DLL only lock
to 1 cycle?