How to make DLL lock to 1 cycle

[paulinesean]

I'm designing a traditional VCDL DLL which
is consist of PD, charge pump and voltage control delay line
, and I take different delay edges from VCDL to form
different delay clocks. However, the DLL can lock to 1 or 2 cycles
or more. The generated different delay clocks are not
what I expect if DLL lock to 2 or more cycles. Is there any way can make DLL only lock
to 1 cycle?

 

[rf_ray]

Please refer to this paper. There is a explaination on your problem

"An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance"

Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim;
Solid-State Circuits, IEEE Journal of , Volume: 35 , Issue: 3 , March 2000
Pages:377 - 384