[SOLVED] How to make Clock Divider

[dadili]

I have to make clock divider from 50MHz to 2.5 Hz. I have no idea how to do it. can someone help me, write the code or explain to me.

 

[RetroTechie]

Welcome dadili,

Forum search function not working? :?:
Changing the frequency

What part are you using? Divisor you state would need some 25 counter bits. In a FPGA that probably wouldn't matter much, but in a CPLD that would be rather wasteful use of chip resources.

 

[Alosevskoy]

Hi! You can create enable ticks for registers in your design which appear with freq 2.5Hz. You need a counter that counts from 0 to 50M/2.5 = 20000000 - 1 = 19_999_999.
In this example module data is written to reg with freq 2.5Hz:

module mymod(clk, data, out);
input clk; // 50MHz
input data;
output reg out;

reg [24:0] cntr; // conter size = log2(20000000-1)
// free-run counter
always@(posedge clk)
if(cntr=19_999_999)
cntr <= 0;
else cntr <= cntr + 1;

wire enable_tick = (cntr == 19_999_999)? 1:0; // create 1 cycle enable ticks with freq 2.5Hz

always@(posedge clk)
if(enable_tick)
out <= data;

endmodule

 

[dadili]

thanks, but I need code which will do that. something like this first one VHDL coding tips and tricks: Clock Frequency converter in VHDL
but i dont understand it
or this one
https://i.imgur.com/lWcyP.gif

 

[TrickyDicky]

what is it you dont understand?

 

[dadili]

to be honest, I dont understand that code, how it works to divide clock

 

[Alosevskoy]

Try to model it :wink: Do not forget to add a reset input or the following initial block:

initial
begin
cntr=0;
out=0;
end

... otherwise you will get X for cntr and out on waveforms. Take a look at the attached waveform. Enable ticks appear with freq 2.5Hz.

The link you've provided describes not a good way of freq dividing.

Good luck!