How to make an LFSR with a loop length of 5 or 10 clock cycles?

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Elephantus

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Hi.

Does anyone know the taps to make an LFSR with a loop length of 5 or 10 clock cycles?

Thanks in advance.
 

Re: LFSR design question

Xilnx has a application note regarding LFSRs (XAPP210). The last section has all the taps for a 3 to 168 clock cycle LFSR. See hxxp://www.xilinx.com/bvdocs/appnotes/xapp210.pdf
 

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    Elephantus

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LFSR design question

LFSR is used in crc computation. so, i guess this should be of some use for u.

**broken link removed**
 

LFSR design question

For Loop Length of 5 take 3 DFF & when value 110 cames it should be connected 2 nand gate through clear of DFF
Thanks
Anmol
 

Re: LFSR design question

just if you have the book

HDL chip design by Douglas Smith.....go through that once

there is a detailed explanation abt LFSR

good luck
 

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