How to make a low ON resistance with NMOS with reasonable length and width

There are always limitations. You may as well start with the
minimum gate length that your target foundry offers. Then
you can find a W that gives you the Ron you want (which
may be insane). Question then is, is "as small as possible"
"as small as practical", or smaller than practical.

You can get really low Ron with a really short L process,
but then fail to meet "off" voltage. Basically L is volts (but
LDMOS can fool you, and longer L in simple MOS device
soon ends up not helping, BVox / reliable Vgs/Vgd),
W/L is Ron (though Tox is in there, co-developed with min L).

You'd be well off to propose a number for "small as possible"
or you will not know when you're done.

What do you mean by "very small" ON resistance?
1 Ohm is small, so might be 10 Ohms depending on the application.
If you are targeting μOhms, then that would obviously lead to impractical values.
For the range of ~0.1mOhms you have reached the domain of discrete devices. Explore the power mosfets of different companies on google.

One suggestion would be to explore other types of MOSFET models.
LDMOS, VDMOS, DMOS etc which might be better suited for low ON resistance applications.
Some foundries provide these as part of their process nodes and we can design using those.
Although, they will not practically give you the 1.86 μOhms that you are targeting.

Power FET gates can be as wide as 10 meters.
The way to "pack" it into a reasonable area is to break a single finger into many fingers of smaller widths (e.g., 10 um or 100 um), to create a multi-finger device.
This is how all power FETs are made.

Hi there,

What exactly is "small RON resistance" That depends on a load / driven component, right? The resistance scales inversely with channel width by definition (L/W ratio) so after a certain W, the decrease of RON will be impractical for a given fabrication technology.

You need really high W/L ratio, but L is limited by technology. In my experience, minimum L is used only in digital logic circuits and maybe some on-chip drivers. If you are designing a "mammoth" device, L should be ~ 10% longer than minimum for fabrication reliability and lowered leakage currents.
Widht can reach millimeters, maybe centimeters.... be careful with stray capacitances in that case.
Layout of such a device can be done as a multi-fingered device with bulk strip every 20 microns or so. There is also a waffle layout... I have also seen polySi gate fluted (corrugated) to squeeze big transistors onto smaller area. This, of course, requires special fabrication technology....

So in short... large W/L, minimized L down to reliable technology limit, W up to technology/practical limit...

Shlooky

Specific resistivity (resistance per micron of gate width) of MOSFETs in on state (in linear regime - large Vgs, small Vdd), is Rsh~1-10 kOhm*um.

So, the device resistance for MOSFET with gate width W is: Rdson=Rsp/W.
Usually, "low Rdson" is few tens of mOhm.
Very low Rdson is single digit mOhm, or less than 1 mOhm.

Also, you must look at it from its context. Any metallization resistance will be larger than your example of uOhms. So sometimes it isn't worth investing area in a low rdson if you'll have comparable (or larger) resistance between your two points of interest.

May I ask what model are you using so that it allows 1nm channel length? That's 5 silicon atoms fyi

Also, maximize VGS and maximize VBS within the reliability limits of the process.