ccw27
Full Member level 5
MOS model for design
Hi,
Given a new process, what do Analog IC designer do before they start using the process for actual design? I am talking about what sort of simulation is typically done beforehand so that a good model is obtained in order to get a good approximation when sizing the transistors? Is Id/W vs. Vgs-Vt plot for different lengths a good model or the good old square law still used?
Thanks
Hi,
Given a new process, what do Analog IC designer do before they start using the process for actual design? I am talking about what sort of simulation is typically done beforehand so that a good model is obtained in order to get a good approximation when sizing the transistors? Is Id/W vs. Vgs-Vt plot for different lengths a good model or the good old square law still used?
Thanks