Mar 8, 2004 #1 A andy2000a Advanced Member level 2 Joined Jul 18, 2001 Messages 597 Helped 14 Reputation 28 Reaction score 8 Trophy points 1,298 Activity points 5,298 as I know , Serial-ATA is 1.5Gbits .. and someone told me , use 750MHz PLL (both edge) for receive it .. but another people told me use 3GHz PLL for locking 1.5G data which architerture is correctly ?? how about 3G-IO design ??
as I know , Serial-ATA is 1.5Gbits .. and someone told me , use 750MHz PLL (both edge) for receive it .. but another people told me use 3GHz PLL for locking 1.5G data which architerture is correctly ?? how about 3G-IO design ??
Jun 23, 2004 #2 K kyrandia Member level 1 Joined Jun 23, 2004 Messages 33 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 286 surely the both arch is right , the 750M's need multi phase (dll) for cdr.