how to make a 3GIO PHY design ???

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andy2000a

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as I know , Serial-ATA is 1.5Gbits ..
and someone told me , use 750MHz PLL (both edge) for receive it ..
but another people told me use 3GHz PLL for locking 1.5G data

which architerture is correctly ??
how about 3G-IO design ??
 

surely the both arch is right , the 750M's need multi phase (dll) for cdr.
 

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